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1. WO2020093519 - MEMORY DEVICE, FABRICATION METHOD THEREFOR, AND ELECTRONIC DEVICE COMPRISING SAME

Publication Number WO/2020/093519
Publication Date 14.05.2020
International Application No. PCT/CN2018/120889
International Filing Date 13.12.2018
IPC
H01L 27/11582 2017.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
10including a plurality of individual components in a repetitive configuration
105including field-effect components
112Read-only memory structures
115Electrically programmable read-only memories; Multistep manufacturing processes therefor
11563with charge-trapping gate insulators, e.g. MNOS or NROM
11578characterised by three-dimensional arrangements, e.g. with cells on different height levels
1158with source and drain on different levels, e.g. with sloping channels
11582the channels comprising vertical portions, e.g. U-shaped channels
CPC
H01L 27/11582
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
10including a plurality of individual components in a repetitive configuration
105including field-effect components
112Read-only memory structures ; [ROM] and multistep manufacturing processes therefor
115Electrically programmable read-only memories; Multistep manufacturing processes therefor
11563with charge-trapping gate insulators, e.g. MNOS or NROM
11578characterised by three-dimensional arrangements, e.g. with cells on different height levels
1158with source and drain on different levels, e.g. with sloping channels
11582the channels comprising vertical portions, e.g. U-shaped channels
H01L 29/40117
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; ; Multistep manufacturing processes therefor
40Electrodes ; ; Multistep manufacturing processes therefor
401Multistep manufacturing processes
4011for data storage electrodes
40117the electrodes comprising a charge-trapping insulator
H01L 29/511
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; ; Multistep manufacturing processes therefor
40Electrodes ; ; Multistep manufacturing processes therefor
43characterised by the materials of which they are formed
49Metal-insulator-semiconductor electrodes, ; e.g. gates of MOSFET
51Insulating materials associated therewith
511with a compositional variation, e.g. multilayer structures
Applicants
  • 中国科学院微电子研究所 INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES [CN]/[CN]
Inventors
  • 朱慧珑 ZHU, Huilong
Agents
  • 中科专利商标代理有限责任公司 CHINA SCIENCE PATENT & TRADEMARK AGENT LTD.
Priority Data
201811336212.109.11.2018CN
Publication Language Chinese (ZH)
Filing Language Chinese (ZH)
Designated States
Title
(EN) MEMORY DEVICE, FABRICATION METHOD THEREFOR, AND ELECTRONIC DEVICE COMPRISING SAME
(FR) DISPOSITIF DE MÉMOIRE, SON PROCÉDÉ DE FABRICATION ET DISPOSITIF ÉLECTRONIQUE LE COMPRENANT
(ZH) 存储器件及其制造方法及包括该存储器件的电子设备
Abstract
(EN)
A memory device, fabrication method therefor, and electronic device comprising same. The memory device may comprise: a substrate (1001); an electrode structure, provided on the substrate (1001) and comprising multiple first electrode layers and multiple second electrode layers which are alternately stacked; multiple vertical active areas penetrating the electrode structure; a first dielectric layer arranged between the vertical active areas and each first electrode layer in the electrode structure; and a second dielectric layer arranged between the vertical active areas and each second electrode layer in the electrode structure, wherein the first dielectric layer and the second dielectric layer respectively construct data storage structures. A first effective work function for the combination of the first electrode layers and the first dielectric layer is thus different from a second effective work function for the combination of the second electrode layers and the second dielectric layer.
(FR)
L'invention concerne un dispositif de mémoire, son procédé de fabrication et un dispositif électronique le comprenant. Le dispositif de mémoire peut comprendre : un substrat (1001) ; une structure d'électrode, disposée sur le substrat (1001) et comprenant de multiples premières couches d'électrode et de multiples secondes couches d'électrode qui sont empilées en alternance ; de multiples zones actives verticales pénétrant dans la structure d'électrode ; une première couche diélectrique disposée entre les zones actives verticales et chaque première couche d'électrode dans la structure d'électrode ; et une seconde couche diélectrique disposée entre les zones actives verticales et chaque seconde couche d'électrode dans la structure d'électrode, la première couche diélectrique et la seconde couche diélectrique construisent respectivement des structures de stockage de données. Une première fonction de travail efficace pour la combinaison des premières couches d'électrode et de la première couche diélectrique est ainsi différente d'une seconde fonction de travail efficace pour la combinaison des secondes couches d'électrode et de la seconde couche diélectrique.
(ZH)
一种存储器件及其制造方法及包括该存储器件的电子设备,该存储器件可以包括:衬底(1001);设置在衬底(1001)上的电极结构,包括交替堆叠的多个第一电极层和多个第二电极层;穿透电极结构的多个竖直有源区;设置在竖直有源区与电极结构中的各第一电极层之间的第一栅介质层以及设置在竖直有源区与电极结构中的各第二电极层之间的第二栅介质层,其中,第一栅介质层和第二栅介质层分别构成数据存储结构。第一电极层与第一栅介质层的组合的第一有效功函数不同于第二电极层与第二栅介质层的组合的第二有效功函数。
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