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1. WO2020092640 - IMPLEMENTING STICKY READ USING ERROR CONTROL SUCCESS RATE ASSOCIATED WITH A MEMORY SUB-SYSTEM

Publication Number WO/2020/092640
Publication Date 07.05.2020
International Application No. PCT/US2019/058955
International Filing Date 30.10.2019
IPC
G11C 29/52 2006.01
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
29Checking stores for correct operation; Testing stores during standby or offline operation
52Protection of memory contents; Detection of errors in memory contents
G11C 29/02 2006.01
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
29Checking stores for correct operation; Testing stores during standby or offline operation
02Detection or location of defective auxiliary circuits, e.g. defective refresh counters
CPC
G11C 16/26
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
16Erasable programmable read-only memories
02electrically programmable
06Auxiliary circuits, e.g. for writing into memory
26Sensing or reading circuits; Data output circuits
G11C 16/3404
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
16Erasable programmable read-only memories
02electrically programmable
06Auxiliary circuits, e.g. for writing into memory
34Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
3404Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells
G11C 2207/2254
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
2207Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
22Control and timing of internal memory operations
2254Calibration
G11C 29/42
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
29Checking stores for correct operation ; ; Subsequent repair; Testing stores during standby or offline operation
04Detection or location of defective memory elements ; , e.g. cell constructio details, timing of test signals
08Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
12Built-in arrangements for testing, e.g. built-in self testing [BIST] ; or interconnection details
38Response verification devices
42using error correcting codes [ECC] or parity check
G11C 29/52
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
29Checking stores for correct operation ; ; Subsequent repair; Testing stores during standby or offline operation
52Protection of memory contents; Detection of errors in memory contents
G11C 7/04
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
7Arrangements for writing information into, or reading information out from, a digital store
04with means for avoiding disturbances due to temperature effects
Applicants
  • MICRON TECHNOLOGY, INC. [US]/[US]
Inventors
  • SINGIDI, Harish
  • MUCHHERLA, Kishore
  • MALSHE, Ashutosh
  • RAYAPROLU, Vamsi
  • RATNAM, Sampath
  • PADILLA, Renato
  • MILLER, Michael
Agents
  • PORTNOVA, Marina
  • KRUEGER, Paul
  • SHEKHER, Rahul
  • SHANGEETA, Rinat
Priority Data
16/177,19331.10.2018US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) IMPLEMENTING STICKY READ USING ERROR CONTROL SUCCESS RATE ASSOCIATED WITH A MEMORY SUB-SYSTEM
(FR) MISE EN OEUVRE D'UNE LECTURE PERSISTANTE À L'AIDE D'UN TAUX DE RÉUSSITE DE CONTRÔLE D'ERREUR ASSOCIÉ À UN SOUS-SYSTÈME DE MÉMOIRE
Abstract
(EN)
A memory sub-system can be determined to be operating within a target operating characteristic based on a threshold success rate associated with error control operations using a particular parameter. Upon determining that the memory sub-system is operating within the target operating characteristic, a sticky read mode is entered by performing subsequent read operations using the particular parameter. It is determined that additional error control operations are triggered for at least a first threshold number of read operations using the particular parameter during the sticky read mode. Upon determining that the additional error control operations are triggered for at least the first threshold number of read operations using the particular parameter during the sticky read mode, the sticky read mode is exited by performing further read operations using a default parameter associated with the memory sub-system.
(FR)
L'invention concerne un sous-système de mémoire qui peut être déterminé pour fonctionner dans une caractéristique de fonctionnement cible sur la base d'un taux de réussite de seuil associé à des opérations de contrôle d'erreur à l'aide d'un paramètre particulier. Lorsqu'il est déterminé que le sous-système de mémoire fonctionne dans la caractéristique de fonctionnement cible, un mode de lecture persistante est entré en effectuant des d'opérations de lecture subséquentes à l'aide du paramètre particulier. Il est déterminé que d'autres opérations de contrôle d'erreur sont déclenchées pour au moins un premier nombre seuil d'opérations de lecture à l'aide du paramètre particulier pendant le mode de lecture persistante. Lors de la détermination du fait que les opérations de contrôle d'erreur supplémentaires sont déclenchées pour au moins le premier nombre seuil d'opérations de lecture à l'aide du paramètre particulier pendant le mode de lecture persistante, le mode de lecture persistante est quitté en effectuant d'autres opérations de lecture à l'aide d'un paramètre par défaut associé au sous-système de mémoire.
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