Processing

Please wait...

Settings

Settings

Goto Application

1. WO2020092624 - MAPPING ENTRY INVALIDATION

Publication Number WO/2020/092624
Publication Date 07.05.2020
International Application No. PCT/US2019/058935
International Filing Date 30.10.2019
IPC
G06F 12/109 2016.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
12Accessing, addressing or allocating within memory systems or architectures
02Addressing or allocation; Relocation
08in hierarchically structured memory systems, e.g. virtual memory systems
10Address translation
109for multiple virtual address spaces, e.g. segmentation
G06F 12/1036 2016.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
12Accessing, addressing or allocating within memory systems or architectures
02Addressing or allocation; Relocation
08in hierarchically structured memory systems, e.g. virtual memory systems
10Address translation
1027using associative or pseudo-associative address translation means, e.g. translation look-aside buffer
1036for multiple virtual address spaces, e.g. segmentation
G06F 13/42 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
13Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
38Information transfer, e.g. on bus
42Bus transfer protocol, e.g. handshake; Synchronisation
CPC
G06F 12/1009
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
12Accessing, addressing or allocating within memory systems or architectures
02Addressing or allocation; Relocation
08in hierarchically structured memory systems, e.g. virtual memory systems
10Address translation
1009using page tables, e.g. page table structures
G06F 13/16
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
13Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
14Handling requests for interconnection or transfer
16for access to memory bus
G06F 13/4282
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
13Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
38Information transfer, e.g. on bus
42Bus transfer protocol, e.g. handshake; Synchronisation
4282on a serial bus, e.g. I2C bus, SPI bus
G06F 2212/657
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
2212Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
65Details of virtual memory and virtual address translation
657Virtual address space management
G06F 2213/0026
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
2213Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
0026PCI express
Applicants
  • HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP [US]/[US]
Inventors
  • WALKER, Shawn K.
  • SHERLOCK, Derek Alan
  • KROEGER, Christopher Shawn
Agents
  • FEBBO, Michael, A.
Priority Data
16/174,73830.10.2018US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) MAPPING ENTRY INVALIDATION
(FR) INVALIDATION D'ENTRÉE DE MAPPAGE
Abstract
(EN)
A memory access system may include a first memory address translator, a second memory address translator and a mapping entry invalidator. The first memory address translator translates a first virtual address in a first protocol of a memory access request to a second virtual address in a second protocol and tracks memory access request completions. The second memory address translator is to translate the second virtual address to a physical address of a memory. The mapping entry invalidator requests invalidation of a first mapping entry of the first mapping address translator requests invalidation of a second mapping entry of the second memory address translator corresponding to the first mapping entry following invalidation of the first mapping entry and based upon the tracked memory access request completions.
(FR)
L'invention concerne un système d'accès à la mémoire pouvant comprendre un premier traducteur d'adresse mémoire, un second traducteur d'adresse mémoire et un dispositif d'invalidation d'entrée de mappage. Le premier traducteur d'adresse mémoire traduit une première adresse virtuelle dans un premier protocole d'une demande d'accès à la mémoire en une seconde adresse virtuelle dans un second protocole et suit des exécutions de demande d'accès à la mémoire. Le second traducteur d'adresse mémoire est destiné à traduire la seconde adresse virtuelle en une adresse physique d'une mémoire. Le dispositif d'invalidation d'entrée de mappage demande une invalidation d'une première entrée de mappage du premier traducteur d'adresse de mappage, demande une invalidation d'une seconde entrée de mappage du second traducteur d'adresse mémoire correspondant à la première entrée de mappage suite à l'invalidation de la première entrée de mappage et sur la base des exécutions de demande d'accès à la mémoire suivies.
Also published as
Latest bibliographic data on file with the International Bureau