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1. WO2020092361 - ARCHITECTURE FOR MONOLITHIC 3D INTEGRATION OF SEMICONDUCTOR DEVICES

Publication Number WO/2020/092361
Publication Date 07.05.2020
International Application No. PCT/US2019/058554
International Filing Date 29.10.2019
IPC
H01L 27/06 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
06including a plurality of individual components in a non-repetitive configuration
H01L 27/088 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
08including only semiconductor components of a single kind
085including field-effect components only
088the components being field-effect transistors with insulated gate
H01L 27/11 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
10including a plurality of individual components in a repetitive configuration
105including field-effect components
11Static random access memory structures
H01L 27/115 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
10including a plurality of individual components in a repetitive configuration
105including field-effect components
112Read-only memory structures
115Electrically programmable read-only memories; Multistep manufacturing processes therefor
CPC
H01L 21/8221
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78with subsequent division of the substrate into plural individual devices
82to produce devices, e.g. integrated circuits, each consisting of a plurality of components
822the substrate being a semiconductor, using silicon technology
8221Three dimensional integrated circuits stacked in different levels
H01L 21/823871
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78with subsequent division of the substrate into plural individual devices
82to produce devices, e.g. integrated circuits, each consisting of a plurality of components
822the substrate being a semiconductor, using silicon technology
8232Field-effect technology
8234MIS technology ; , i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
8238Complementary field-effect transistors, e.g. CMOS
823871interconnection or wiring or contact manufacturing related aspects
H01L 23/5226
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
52Arrangements for conducting electric current within the device in operation from one component to another ; , i.e. interconnections, e.g. wires, lead frames
522including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
5226Via connections in a multilevel interconnection structure
H01L 23/5286
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
52Arrangements for conducting electric current within the device in operation from one component to another ; , i.e. interconnections, e.g. wires, lead frames
522including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
528Geometry or; layout of the interconnection structure
5286Arrangements of power or ground buses
H01L 27/0688
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
06including a plurality of individual components in a non-repetitive configuration
0688Integrated circuits having a three-dimensional layout
H01L 27/092
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
08including only semiconductor components of a single kind
085including field-effect components only
088the components being field-effect transistors with insulated gate
092complementary MIS field-effect transistors
Applicants
  • TOKYO ELECTRON LIMITED [JP]/[JP]
  • TOKYO ELECTRON U.S. HOLDINGS [US]/[US] (JP)
Inventors
  • LIEBMANN, Lars
  • SMITH, Jeffrey
  • DEVILLIERS, Anton, J.
Agents
  • GARLEPP, Edwin, D.
  • MASON, J., Derek
Priority Data
62/752,11229.10.2018US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) ARCHITECTURE FOR MONOLITHIC 3D INTEGRATION OF SEMICONDUCTOR DEVICES
(FR) ARCHITECTURE POUR L'INTÉGRATION MONOLITHIQUE EN TROIS DIMENSIONS DE DISPOSITIFS À SEMI-CONDUCTEURS
Abstract
(EN)
A three-dimensional (3D) integrated circuit (IC) includes a substrate having a substrate surface, a power rail provided in the substrate, and a first tier of semiconductor devices provided in the substrate and positioned over the power rail along a thickness direction of the substrate. A wiring tier is provided in the substrate, and a second tier of semiconductor devices is provided in the substrate and positioned over the wiring tier along the thickness direction. The second tier of semiconductor devices is stacked on the first tier of semiconductor devices in the thickness direction such that the wiring tier is interposed between the first and second tiers of semiconductor devices. A first vertical interconnect structure extends downward from the wiring tier to the first tier of semiconductor devices to electrically connect the wiring tier to a device within the first tier of semiconductor devices. A second vertical interconnect structure extends upward from the wiring tier to the second tier of semiconductor devices to electrically connect the wiring tier to a device within the second tier of semiconductor devices.
(FR)
La présente invention concerne un circuit intégré (CI) en trois dimensions (3D) comprenant un substrat ayant une surface de substrat, un rail d'alimentation placé dans le substrat, et un premier niveau de dispositifs à semi-conducteurs placés dans le substrat et positionnés sur le rail d'alimentation le long d'une direction d'épaisseur du substrat. Un niveau de câblage est placé dans le substrat, et un second niveau de dispositifs à semi-conducteurs est placé dans le substrat et positionné sur le niveau de câblage le long de la direction de l'épaisseur. Le second niveau de dispositifs à semi-conducteurs est empilé sur le premier niveau de dispositifs à semi-conducteurs dans la direction de l'épaisseur de telle sorte que le niveau de câblage est interposé entre les premier et second niveaux de dispositifs à semi-conducteurs. Une première structure d'interconnexion verticale s'étend vers le bas du niveau de câblage au premier niveau de dispositifs à semi-conducteurs pour connecter électriquement le niveau de câblage à un dispositif à l'intérieur du premier niveau de dispositifs à semi-conducteurs. Une seconde structure d'interconnexion verticale s'étend vers le haut du niveau de câblage au second niveau de dispositifs à semi-conducteurs pour connecter électriquement le niveau de câblage à un dispositif à l'intérieur du second niveau de dispositifs à semi-conducteurs.
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