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1. WO2020091771 - MEMORY INTERFACE FOR A SECURE NOR FLASH MEMORY

Publication Number WO/2020/091771
Publication Date 07.05.2020
International Application No. PCT/US2018/058556
International Filing Date 31.10.2018
IPC
G06F 3/06 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
3Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
06Digital input from, or digital output to, record carriers
G06F 12/14 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
12Accessing, addressing or allocating within memory systems or architectures
14Protection against unauthorised use of memory
G06F 21/00 2013.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
21Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
Applicants
  • REDPINE SIGNALS, INC. [US]/[US]
Inventors
  • MURALI, Partha Sarathy
  • PULAGAM, Venkata Siva Prasad
  • SANKABATHULA, Sailaja Dharani Naga
  • GUNTURU, Venkat Rao
  • KALLAM, Subba Reddy
Agents
  • CHESAVAGE, Jay A.
Priority Data
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) MEMORY INTERFACE FOR A SECURE NOR FLASH MEMORY
(FR) INTERFACE DE MÉMOIRE POUR MÉMOIRE FLASH NON-OU SÉCURISÉE
Abstract
(EN)
A flash memory controller is operative to receive serial commands and command arguments. A flash permissions table identifies each segment of flash memory as READ_ONLY, PRIVATE_R/W or OPEN_R/W. A memory interface is coupled to a flash memory and also the flash permissions table. When a flash memory write operation is received with an associated command argument corresponding to an address indicated as READ_ONLY in the flash permissions table and a DISABLE_WR_REG is true, the write operation is ignored or converted into a non-write command and issued to the flash memory.
(FR)
Un contrôleur de mémoire flash est conçu pour recevoir des commandes série et des arguments de commande. Une table d'autorisations flash identifie chaque segment de mémoire flash en tant que READ_ONLY, PRIVATE_R/W ou OPEN_R/W. Une interface de mémoire est couplée à une mémoire flash et également à la table d'autorisations flash. Lorsqu'une opération d'écriture de mémoire flash est reçue avec un argument de commande associé correspondant à une adresse indiquée en tant que READ_ONLY dans la table d’autorisations flash et qu’un DISABLE_WR_REG est vrai, l'opération d'écriture est ignorée ou convertie en une commande de non-écriture et transmise à la mémoire flash.
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