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1. WO2020088208 - WAFER STACKING METHOD AND WAFER STACKING STRUCTURE

Publication Number WO/2020/088208
Publication Date 07.05.2020
International Application No. PCT/CN2019/110399
International Filing Date 10.10.2019
IPC
H01L 25/065 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25Assemblies consisting of a plurality of individual semiconductor or other solid state devices
03all the devices being of a type provided for in the same subgroup of groups H01L27/-H01L51/128
04the devices not having separate containers
065the devices being of a type provided for in group H01L27/78
H01L 21/98 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
98Assembly of devices consisting of solid state components formed in or on a common substrate; Assembly of integrated circuit devices
Applicants
  • CHANGXIN MEMORY TECHNOLOGIES, INC. [CN]/[CN]
Inventors
  • CHUANG, Ling-Yi
  • NING, Shu-Liang
Agents
  • SHANGHAI SAVVY INTELLECTUAL PROPERTY AGENCY
Priority Data
201811295887.601.11.2018CN
201821793680.701.11.2018CN
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) WAFER STACKING METHOD AND WAFER STACKING STRUCTURE
(FR) PROCÉDÉ D'EMPILEMENT DE TRANCHES ET STRUCTURE D'EMPILEMENT DE TRANCHES
Abstract
(EN)
A wafer stacking method and structure are provided. The wafer stacking method includes: providing a first wafer having an upper surface comprising a first bonding pad configured to connect to a first signal; fabricating a first lower redistribution layer (RDL) and a first upper RDL on the first wafer, with the first lower RDL including a first wiring connected to the first bonding pad, the first upper RDL including a second wiring connected to the first wiring, and the second wiring having a first landing pad; bonding a second wafer on the first upper RDL, wherein an upper surface of the second wafer includes a second bonding pad configured to connect to a second signal and located corresponding to the first bonding pad; and fabricating a first through silicon via (TSV) connected to the first landing pad. The wafer stacking method improves the manufacturing yield of a die.
(FR)
L'invention concerne un procédé et une structure d'empilement de tranches. Le procédé d'empilement de tranches comprend : la fourniture d'une première tranche ayant une surface supérieure comprenant un premier plot de connexion configuré pour se connecter à un premier signal ; la fabrication d'une première couche de redistribution inférieure (RDL) et une première RDL supérieure sur la première tranche, la première RDL inférieure comprenant un premier câblage connecté au premier plot de connexion, la première RDL supérieure comprenant un second câblage connecté au premier câblage, et le second câblage ayant un premier plot d'accueil ; la connexion d'une seconde tranche sur la première RDL supérieure, une surface supérieure de la seconde tranche comprenant un second plot de connexion configuré pour se connecter à un second signal et situé en correspondance avec le premier plot de connexion ; et la fabrication d'un premier via traversant (TSV) connecté au premier plot d'accueil. Le procédé d'empilement de tranches améliore le rendement de fabrication d'une matrice.
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