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1. WO2020072952 - SYSTEMS, METHODS, AND APPARATUS TO DETECT ADDRESS FAULTS

Publication Number WO/2020/072952
Publication Date 09.04.2020
International Application No. PCT/US2019/054784
International Filing Date 04.10.2019
IPC
G06F 11/08 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
11Error detection; Error correction; Monitoring
07Responding to the occurrence of a fault, e.g. fault tolerance
08Error detection or correction by redundancy in data representation, e.g. by using checking codes
G06F 11/10 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
11Error detection; Error correction; Monitoring
07Responding to the occurrence of a fault, e.g. fault tolerance
08Error detection or correction by redundancy in data representation, e.g. by using checking codes
10Adding special bits or symbols to the coded information, e.g. parity check, casting out nines or elevens
H03M 13/09 2006.01
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
MCODING, DECODING OR CODE CONVERSION, IN GENERAL
13Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
03Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
05using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
09Error detection only, e.g. using cyclic redundancy check codes or single parity bit
CPC
G06F 11/0721
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
11Error detection; Error correction; Monitoring
07Responding to the occurrence of a fault, e.g. fault tolerance
0703Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
0706the processing taking place on a specific hardware platform or in a specific software environment
0721within a central processing unit [CPU]
G06F 11/0763
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
11Error detection; Error correction; Monitoring
07Responding to the occurrence of a fault, e.g. fault tolerance
0703Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
0751Error or fault detection not based on redundancy
0763by bit configuration check, e.g. of formats or tags
G06F 11/1016
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
11Error detection; Error correction; Monitoring
07Responding to the occurrence of a fault, e.g. fault tolerance
08Error detection or correction by redundancy in data representation, e.g. by using checking codes
10Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
1008in individual solid state devices
1012using codes or arrangements adapted for a specific type of error
1016Error in accessing a memory location, i.e. addressing error
G06F 11/1044
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
11Error detection; Error correction; Monitoring
07Responding to the occurrence of a fault, e.g. fault tolerance
08Error detection or correction by redundancy in data representation, e.g. by using checking codes
10Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
1008in individual solid state devices
1044with specific ECC/EDC distribution
G06F 11/1076
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
11Error detection; Error correction; Monitoring
07Responding to the occurrence of a fault, e.g. fault tolerance
08Error detection or correction by redundancy in data representation, e.g. by using checking codes
10Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
1076Parity data used in redundant arrays of independent storages, e.g. in RAID systems
Applicants
  • TEXAS INSTRUMENTS INCORPORATED [US]/[US]
  • TEXAS INSTRUMENTS JAPAN LIMITED [JP]/[JP] (JP)
Inventors
  • FOLEY, David, Peter
Agents
  • ABRAHAM, Ebby
Common Representative
  • TEXAS INSTRUMENTS INCORPORATED
Priority Data
16/153,54605.10.2018US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) SYSTEMS, METHODS, AND APPARATUS TO DETECT ADDRESS FAULTS
(FR) SYSTÈMES, PROCÉDÉS ET APPAREIL DE DÉTECTION D'ERREURS D'ADRESSE
Abstract
(EN)
Methods, apparatus, systems and articles of manufacture are disclosed for safety mechanisms to actively detect address faults. An example system includes a first parity generator (112), a second parity generator (128), and a parity checker (116). The first parity generator (112) is to generate a first parity based on a first address information. The first address information corresponds to a desired location to store data in a memory storage array (124). The second parity generator (128) is to generate a second parity based on a second address information. The second address information corresponding to an actual location where the data is stored in the memory storage array (124). The parity checker (116) is to compare the first parity and the second parity to detect a fault.
(FR)
L'invention concerne des procédés, un appareil, des systèmes et des articles de fabrication pour que des mécanismes de sécurité détectent activement des erreurs d'adresse. Un système illustratif contient un premier générateur de parité (112), un deuxième générateur de parité (128), et un vérificateur de parité (116). Le premier générateur de parité (112) sert à produire une première parité en fonction d'une première information d'adresse. La première information d'adresse correspond à un emplacement souhaité où stocker des données dans une matrice de mémoire (124). Le deuxième générateur de parité (128) sert à produire une deuxième parité en fonction d'une deuxième information d'adresse. La deuxième information d'adresse correspond à un emplacement réel où les données sont stockées dans la matrice de mémoire (124). Le vérificateur de parité (116) sert à comparer la première parité et la deuxième parité pour détecter une erreur.
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