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1. WO2020072462 - ACCESS UNIT AND MANAGEMENT SEGMENT MEMORY OPERATIONS

Publication Number WO/2020/072462
Publication Date 09.04.2020
International Application No. PCT/US2019/054019
International Filing Date 01.10.2019
IPC
G06F 3/06 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
3Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
06Digital input from, or digital output to, record carriers
G06F 12/06 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
12Accessing, addressing or allocating within memory systems or architectures
02Addressing or allocation; Relocation
06Addressing a physical block of locations, e.g. base addressing, module addressing, address space extension, memory dedication
G06F 12/08 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
12Accessing, addressing or allocating within memory systems or architectures
02Addressing or allocation; Relocation
08in hierarchically structured memory systems, e.g. virtual memory systems
CPC
G06F 12/0246
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
12Accessing, addressing or allocating within memory systems or architectures
02Addressing or allocation; Relocation
0223User address space allocation, e.g. contiguous or non contiguous base addressing
023Free address space management
0238Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
0246in block erasable memory, e.g. flash memory
G06F 12/0284
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
12Accessing, addressing or allocating within memory systems or architectures
02Addressing or allocation; Relocation
0223User address space allocation, e.g. contiguous or non contiguous base addressing
0284Multiple user address space allocation, e.g. using different base addresses
G06F 12/0292
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
12Accessing, addressing or allocating within memory systems or architectures
02Addressing or allocation; Relocation
0223User address space allocation, e.g. contiguous or non contiguous base addressing
0292using tables or multilevel address translation means
G06F 12/10
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
12Accessing, addressing or allocating within memory systems or architectures
02Addressing or allocation; Relocation
08in hierarchically structured memory systems, e.g. virtual memory systems
10Address translation
G06F 2212/1016
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
2212Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
10Providing a specific technical effect
1016Performance improvement
G06F 2212/1036
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
2212Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
10Providing a specific technical effect
1032Reliability improvement, data loss prevention, degraded operation etc
1036Life time enhancement
Applicants
  • MICRON TECHNOLOGY, INC. [US]/[US]
Inventors
  • MCGLAUGHLIN, Edward C.
  • LUCAS, Gary J.
  • JEDDELOH, Joseph M.
Agents
  • SCHOFIELD, Andy L.
Priority Data
16/149,96102.10.2018US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) ACCESS UNIT AND MANAGEMENT SEGMENT MEMORY OPERATIONS
(FR) UNITÉ D'ACCÈS ET OPÉRATIONS DE MÉMOIRE DE SEGMENT DE GESTION
Abstract
(EN)
A system includes a first memory component having a particular access size associated with performance of memory operations, a second memory component to store a logical to physical data structure whose entries map management segments to respective physical locations in the memory component, wherein each management segment corresponds to an aggregated plurality of logical access units having the particular access size, and a processing device, operably coupled to the memory component. The processing device can perform memory management operations on a per management segment basis by: for each respective management segment, tracking access requests to constituent access units corresponding to the respective management segment, and determining whether to perform a particular memory management operation on the respective management segment based on the tracking.
(FR)
L'invention concerne un système comprenant un premier composant de mémoire doté d'une taille d'accès particulière associée à la réalisation d'opérations de mémoire, un deuxième composant de mémoire destiné à stocker une structure de données logique à physique dont les entrées mappent des segments de gestion sur des emplacements physiques respectifs dans le composant de mémoire, chaque segment de gestion correspondant à une pluralité agrégée d'unités d'accès logiques dotées de la taille d'accès donnée, ainsi qu'un dispositif de traitement couplé fonctionnel au composant de mémoire. Le dispositif de traitement peut effectuer des opérations de gestion de mémoire sur une base par segment de gestion, consistant : pour chaque segment de gestion respectif, à suivre des demandes d'accès à des unités d'accès constitutives correspondant au segment de gestion respectif, et à déterminer s'il faut effectuer une opération de gestion de mémoire donnée sur le segment de gestion respectif, en fonction de ce suivi.
Also published as
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