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1. WO2020072106 - TURBO DECODER WITH REDUCED PROCESSING AND MINIMAL RE-TRANSMISSION

Publication Number WO/2020/072106
Publication Date 09.04.2020
International Application No. PCT/US2019/037116
International Filing Date 13.06.2019
IPC
H03M 13/11 2006.01
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
MCODING, DECODING OR CODE CONVERSION, IN GENERAL
13Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
03Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
05using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
11using multiple parity bits
H03M 13/27 2006.01
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
MCODING, DECODING OR CODE CONVERSION, IN GENERAL
13Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
27using interleaving techniques
H03M 13/00 2006.01
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
MCODING, DECODING OR CODE CONVERSION, IN GENERAL
13Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
H04L 1/00 2006.01
HELECTRICITY
04ELECTRIC COMMUNICATION TECHNIQUE
LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
1Arrangements for detecting or preventing errors in the information received
CPC
H03M 13/09
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
MCODING; DECODING; CODE CONVERSION IN GENERAL
13Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
03Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
05using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
09Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
H03M 13/2957
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
MCODING; DECODING; CODE CONVERSION IN GENERAL
13Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
29combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
2957Turbo codes and decoding
H03M 13/3769
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
MCODING; DECODING; CODE CONVERSION IN GENERAL
13Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
37Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
3769using symbol combining, e.g. Chase combining of symbols received twice or more
H03M 13/6306
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
MCODING; DECODING; CODE CONVERSION IN GENERAL
13Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
63Joint error correction and other techniques
6306Error control coding in combination with Automatic Repeat reQuest [ARQ] and diversity transmission, e.g. coding schemes for the multiple transmission of the same information or the transmission of incremental redundancy
H04L 1/00
HELECTRICITY
04ELECTRIC COMMUNICATION TECHNIQUE
LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
1Arrangements for detecting or preventing errors in the information received
Applicants
  • JOHN MEZZALINGUA ASSOCIATES, LLC D/B/A JMA WIRELESS [US]/[US]
Inventors
  • BRYANT, Rodney
  • TURNER, Stephen
  • MASTERS, Jeffrey
Agents
  • RAHMAN, Ashek M.
Priority Data
62/739,44201.10.2018US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) TURBO DECODER WITH REDUCED PROCESSING AND MINIMAL RE-TRANSMISSION
(FR) TURBO-DÉCODEUR À TRAITEMENT RÉDUIT ET RETRANSMISSION MINIMALE
Abstract
(EN)
Disclosed is a method for processing code blocks as implemented by a baseband processor. The method involves performing a cyclic redundancy check on decoded and deinterleaved code blocks until one fails its CRC check. On first failure the baseband processor requests a retransmission of the code blocks and resumes CRC checks on the retransmitted code blocks, beginning at the code block that had failed. In the event of subsequent failures, the baseband processor performs a soft combine on the failed retransmitted block with its original transmitted counterpart. Only if the soft combined code block fails does the baseband processor request another retransmission. In this case, subsequent CRC failures result in soft combines of three corresponding code words, making the process more robust. The method reduces the number of retransmissions as well as the computing resources needed for processing incoming code blocks.
(FR)
L'invention concerne un procédé de traitement de blocs de code tel que mis en œuvre par un processeur de bande de base. Le procédé consiste à effectuer une vérification de redondance cyclique sur des blocs de code décodés et désentrelacés jusqu'à ce que l'un échoue à la vérification CRC. Lors d'une première défaillance, le processeur de bande de base demande une retransmission des blocs de code et reprend les vérifications CRC sur les blocs de code retransmis, commençant au niveau du bloc de code qui a échoué. Dans le cas de défaillances ultérieures, le processeur de bande de base effectue une combinaison souple sur le bloc retransmis défaillant avec sa contrepartie transmise d'origine. Le processeur de bande de base ne demande une autre retransmission que si le bloc de code combiné souple échoue. Dans ce cas, des échecs de CRC ultérieurs conduisent à des combinaisons souples de trois mots de code correspondants, ce qui rend le processus plus robuste. Le procédé réduit le nombre de retransmissions ainsi que les ressources informatiques nécessaires au traitement de blocs de code entrant.
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