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1. WO2020070986 - METHOD FOR MANUFACTURING SEMICONDUCTOR ELEMENT AND SEMICONDUCTOR SUBSTRATE

Publication Number WO/2020/070986
Publication Date 09.04.2020
International Application No. PCT/JP2019/032217
International Filing Date 19.08.2019
IPC
H01L 21/02 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
H01L 21/20 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18the devices having semiconductor bodies comprising elements of group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
20Deposition of semiconductor materials on a substrate, e.g. epitaxial growth
CPC
H01L 21/02
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
H01L 21/20
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
18the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
20Deposition of semiconductor materials on a substrate, e.g. epitaxial growth ; solid phase epitaxy
Applicants
  • 株式会社フィルネックス FILNEX INC. [JP]/[JP]
Inventors
  • 荻原 光彦 OGIHARA Mitsuhiko
Agents
  • 泉 通博 IZUMI Michihiro
Priority Data
2018-18728602.10.2018JP
Publication Language Japanese (JA)
Filing Language Japanese (JA)
Designated States
Title
(EN) METHOD FOR MANUFACTURING SEMICONDUCTOR ELEMENT AND SEMICONDUCTOR SUBSTRATE
(FR) PROCÉDÉ DE FABRICATION D'UN ÉLÉMENT SEMI-CONDUCTEUR, ET SUBSTRAT SEMI-CONDUCTEUR
(JA) 半導体素子の製造方法及び半導体基板
Abstract
(EN)
This method for manufacturing a semiconductor element includes: a bonding layer forming step for forming a bonding layer 102 that bonds a semiconductor thin film with a weaker force than a covalent bond in a bonding layer region which is a portion of a first substrate 101; a thin film forming step for forming a semiconductor thin film 103 in the bonding layer region and a bonding layer absent region constituting the portion of the first substrate 101 other than the bonding layer region; a separating step for separating the semiconductor thin film 103 from the first substrate 101 by bonding an organic layer of a pickup substrate 140 different from the first substrate 101 to the semiconductor thin film 103; an attachment removing step for removing the bonding layer 102 attached to a release surface of the semiconductor thin film 103 after being separated from the first substrate 101; and a connecting step for connecting the semiconductor thin film 103 after removal of a bonding layer 122 to a second substrate 201 that is different from the first substrate 101.
(FR)
La présente invention porte sur un procédé de fabrication d'un élément semi-conducteur, comprenant : une étape de formation de couche de liaison consistant à former une couche de liaison (102) qui lie un film mince semi-conducteur au moyen d'une force plus faible qu'une liaison covalente dans une région de couche de liaison qui est une partie d'un premier substrat (101) ; une étape de formation de film mince consistant former un film mince semi-conducteur (103) dans la région de couche de liaison et une région exempte de couche de liaison constituant la partie du premier substrat (101) autre que la région de couche de liaison ; une étape de séparation consistant séparer le film mince semi-conducteur (103) du premier substrat (101) en liant une couche organique d'un substrat de saisi (140) différent du premier substrat (101) au film mince semi-conducteur (103) ; une étape d'élimination de fixation consistant éliminer la couche de liaison (102) fixée à une surface de libération du film mince semi-conducteur (103) après avoir été séparé du premier substrat (101) ; et une étape de connexion consistant connecter le film mince semi-conducteur (103) après élimination d'une couche de liaison (122) à un second substrat (201) qui est différent du premier substrat (101).
(JA)
半導体素子の製造方法は、第1基板101の一部の結合層領域に、共有結合よりも弱い力で半導体薄膜を結合する結合層102を形成する結合層形成工程と、結合層領域及び結合層領域以外の非結合層領域に半導体薄膜103を形成する薄膜形成工程と、第1基板101と異なるピックアップ基板140が有する有機物層を半導体薄膜103に結合することにより、第1基板101から半導体薄膜103を分離する分離工程と、第1基板101から分離した後の半導体薄膜103の剥離面に付着した結合層102を除去する付着物除去工程と、第1基板101と異なる第2基板201に結合層122を除去した後の半導体薄膜103を接合する接合工程と、を有する。
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