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1. WO2020068354 - DATA TRANSFER IN PORT SWITCH MEMORY

Publication Number WO/2020/068354
Publication Date 02.04.2020
International Application No. PCT/US2019/048820
International Filing Date 29.08.2019
IPC
G11C 8/16 2006.01
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
8Arrangements for selecting an address in a digital store
16Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
G11C 7/10 2006.01
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
7Arrangements for writing information into, or reading information out from, a digital store
10Input/output data interface arrangements, e.g. I/O data control circuits, I/O data buffers
CPC
G06F 11/201
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
11Error detection; Error correction; Monitoring
07Responding to the occurrence of a fault, e.g. fault tolerance
16Error detection or correction of the data by redundancy in hardware
20using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
2002where interconnections or communication control functionality are redundant
2007using redundant communication media
201between storage system components
G06F 12/0868
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
12Accessing, addressing or allocating within memory systems or architectures
02Addressing or allocation; Relocation
08in hierarchically structured memory systems, e.g. virtual memory systems
0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
0866for peripheral storage systems, e.g. disk cache
0868Data transfer between cache memory and other subsystems, e.g. storage devices or host systems
G06F 12/0897
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
12Accessing, addressing or allocating within memory systems or architectures
02Addressing or allocation; Relocation
08in hierarchically structured memory systems, e.g. virtual memory systems
0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
0893Caches characterised by their organisation or structure
0897with two or more cache hierarchy levels
G06F 13/1668
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
13Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
14Handling requests for interconnection or transfer
16for access to memory bus
1668Details of memory controller
G06F 3/0635
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
3Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
06Digital input from or digital output to record carriers, ; e.g. RAID, emulated record carriers, networked record carriers
0601Dedicated interfaces to storage systems
0628making use of a particular technique
0629Configuration or reconfiguration of storage systems
0635by changing the path, e.g. traffic rerouting, path reconfiguration
G06F 3/0655
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
3Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
06Digital input from or digital output to record carriers, ; e.g. RAID, emulated record carriers, networked record carriers
0601Dedicated interfaces to storage systems
0628making use of a particular technique
0655Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
Applicants
  • MICRON TECHNOLOGY, INC. [US]/[US]
Inventors
  • ROSS, Frank F.
Agents
  • KERN, Jacob T.
Priority Data
16/139,58624.09.2018US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) DATA TRANSFER IN PORT SWITCH MEMORY
(FR) TRANSFERT DE DONNÉES DANS UNE MÉMOIRE À COMMUTATEUR DE PORT
Abstract
(EN)
The present disclosure includes apparatuses and methods related to data transfer in memory. An example apparatus can include a first number of memory devices coupled to a host via a first number of ports and a second number of memory devices coupled to the first number of memory device via a second number of ports, wherein a first number of commands are executed to transfer data between the first number of memory devices and the host via the first number of ports and a second number of commands are executed to transfer data between the first number of memory device and the second number of memory device via the second number of ports.
(FR)
La présente invention concerne des appareils et des procédés relatifs à un transfert de données dans une mémoire. Un appareil donné à titre d'exemple peut comprendre un premier nombre de dispositifs de mémoire couplés à un hôte par l'intermédiaire d'un premier nombre de ports et un second nombre de dispositifs de mémoire couplés au premier nombre de dispositifs de mémoire par l'intermédiaire d'un second nombre de ports, un premier nombre de commandes étant exécutées pour transférer des données entre le premier nombre de dispositifs de mémoire et l'hôte par l'intermédiaire du premier nombre de ports et un second nombre de commandes étant exécutées pour transférer des données entre le premier nombre de dispositifs de mémoire et le second nombre de dispositifs de mémoire par l'intermédiaire du second nombre de ports.
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