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1. WO2020068240 - DUAL POWER I/O RECEIVER

Publication Number WO/2020/068240
Publication Date 02.04.2020
International Application No. PCT/US2019/040023
International Filing Date 29.06.2019
IPC
G11C 11/4074 2006.01
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21using electric elements
34using semiconductor devices
40using transistors
401forming cells needing refreshing or charge regeneration, i.e. dynamic cells
4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
407for memory cells of the field-effect type
4074Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
G11C 5/14 2006.01
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
5Details of stores covered by group G11C11/63
14Power supply arrangements
CPC
G06F 1/3275
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
1Details not covered by groups G06F3/00G06F13/00 and G06F21/00
26Power supply means, e.g. regulation thereof
32Means for saving power
3203Power management, i.e. event-based initiation of power-saving mode
3234Power saving characterised by the action undertaken
325Power saving in peripheral device
3275Power saving in memory, e.g. RAM, cache
G06F 13/1694
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
13Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
14Handling requests for interconnection or transfer
16for access to memory bus
1668Details of memory controller
1694Configuration of memory controller to different memory types
G11C 7/1051
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
7Arrangements for writing information into, or reading information out from, a digital store
10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
1051Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
G11C 7/1087
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
7Arrangements for writing information into, or reading information out from, a digital store
10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
1078Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
1087Data input latches
Applicants
  • INTEL CORPORATION [US]/[US]
Inventors
  • MOSTOFA, Mohammed
  • CHENG, Roger K.
  • MARTIN, Aaron
  • MOZAK, Christopher
  • KAPPANGANTULA, Pavan Kumar
  • YANG, Hsien-Pao
Agents
  • MUGHAL, Usman A.
Priority Data
16/147,63529.09.2018US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) DUAL POWER I/O RECEIVER
(FR) RÉCEPTEUR D'E/S À DOUBLE ALIMENTATION
Abstract
(EN)
An apparatus is provided which comprises: a first circuitry to sample a first input signal to generate a first sampled signal, and to sample a second input signal to generate a second sampled signal, wherein the first input signal comprises data; a second circuitry to receive the first sampled signal and the second sampled signal, and to generate a first pair of differential signals; an offset cancellation circuitry to cancel or reduce an offset in the first pair of differential signals; and a latch to receive the first pair of differential signals subsequent to the cancellation or reduction of the offset, and to output a second pair of differential signals, wherein the second pair of differential signals is indicative of the data.
(FR)
L'invention concerne un appareil qui comprend : un premier circuit pour échantillonner un premier signal d'entrée afin de générer un premier signal échantillonné, et pour échantillonner un second signal d'entrée afin de générer un second signal échantillonné, le premier signal d'entrée comprenant des données ; un second circuit pour recevoir le premier signal échantillonné et le second signal échantillonné, et pour générer une première paire de signaux différentiels ; un circuit d'annulation de décalage pour annuler ou réduire un décalage dans la première paire de signaux différentiels ; et un verrou pour recevoir la première paire de signaux différentiels suite à l'annulation ou à la réduction du décalage, et pour délivrer en sortie une seconde paire de signaux différentiels, la seconde paire de signaux différentiels étant indicative des données.
Also published as
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