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1. WO2020068206 - A DUTY CYCLE CORRECTION SYSTEM AND LOW DROPOUT (LDO) REGULATOR BASED DELAY-LOCKED LOOP (DLL)

Publication Number WO/2020/068206
Publication Date 02.04.2020
International Application No. PCT/US2019/039061
International Filing Date 25.06.2019
IPC
H03K 5/156 2006.01
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
KPULSE TECHNIQUE
5Manipulation of pulses not covered by one of the other main groups of this subclass
156Arrangements in which a continuous pulse train is transformed into a train having a desired pattern
G05F 1/575 2006.01
GPHYSICS
05CONTROLLING; REGULATING
FSYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
1Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
10Regulating voltage or current
46wherein the variable actually regulated by the final control device is dc
56using semiconductor devices in series with the load as final control devices
575characterised by the feedback circuit
H03L 7/081 2006.01
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
7Automatic control of frequency or phase; Synchronisation
06using a reference signal applied to a frequency- or phase-locked loop
08Details of the phase-locked loop
081provided with an additional controlled phase shifter
G06F 1/08 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
1Details not covered by groups G06F3/-G06F13/82
04Generating or distributing clock signals or signals derived directly therefrom
08Clock generators with changeable or programmable clock frequency
CPC
G06F 1/08
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
1Details not covered by groups G06F3/00G06F13/00 and G06F21/00
04Generating or distributing clock signals or signals derived directly therefrom
08Clock generators with changeable or programmable clock frequency
G11C 29/023
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
29Checking stores for correct operation ; ; Subsequent repair; Testing stores during standby or offline operation
02Detection or location of defective auxiliary circuits, e.g. defective refresh counters
023in clock generator or timing circuitry
G11C 29/028
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
29Checking stores for correct operation ; ; Subsequent repair; Testing stores during standby or offline operation
02Detection or location of defective auxiliary circuits, e.g. defective refresh counters
028with adaption or trimming of parameters
G11C 7/1057
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
7Arrangements for writing information into, or reading information out from, a digital store
10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
1051Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
1057Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
G11C 7/1066
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
7Arrangements for writing information into, or reading information out from, a digital store
10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
1051Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
1066Output synchronization
G11C 7/1084
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
7Arrangements for writing information into, or reading information out from, a digital store
10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
1078Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
1084Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
Applicants
  • INTEL CORPORATION [US]/[US]
Inventors
  • MARTIN, Aaron
  • CHENG, Roger
  • VENKATRAMANI, Hari
  • DOUR, Navneet
  • MANSURI, Mozhgan
  • CASPER, Bryan
  • O'MAHONY, Frank
  • BALAMURUGAN, Ganesh
  • BALANKUTTY, Ajay
  • ZHOU, Kuan
  • TIRUMALAI, Sridhar
  • VENKATARAMANA, Krishnamurthy
  • THOMAS, Alex
  • NGUYEN, Quoc
Agents
  • MUGHAL, Usman A.
Priority Data
16/144,94927.09.2018US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) A DUTY CYCLE CORRECTION SYSTEM AND LOW DROPOUT (LDO) REGULATOR BASED DELAY-LOCKED LOOP (DLL)
(FR) SYSTÈME DE CORRECTION DE RAPPORT CYCLIQUE ET BOUCLE À VERROUILLAGE DE RETARD (DLL) À BASE DE RÉGULATEUR À FAIBLE CHUTE DE TENSION (LDO)
Abstract
(EN)
An apparatus is provided, where the apparatus includes a plurality of components; a first circuitry to generate a clock signal, and to supply the clock signal to the plurality of components; a second circuitry to estimate, for each of two or more components of the plurality of components, a corresponding duty cycle of the clock signal received at the corresponding component, wherein two or more duty cycles corresponding to the two or more components are determined; a third circuitry to determine an average of the two or more duty cycles; and a fourth circuitry to correct a duty cycle of the clock signal generated by the first circuitry, based at least in part on the average.
(FR)
L'invention concerne un appareil, l'appareil comprenant une pluralité de composants ; un premier circuit pour générer un signal d'horloge, et pour fournir le signal d'horloge à la pluralité de composants ; un second circuit pour estimer, pour chacun des deux ou plus composants de la pluralité de composants, un rapport cyclique correspondant du signal d'horloge reçu au niveau du composant correspondant, au moins deux rapports cycliques correspondant aux deux ou plus de deux composants étant déterminés ; un troisième circuit pour déterminer une moyenne des deux ou plus de deux rapports cycliques ; et un quatrième circuit pour corriger un rapport cyclique du signal d'horloge généré par le premier circuit, sur la base, au moins en partie, de la moyenne.
Also published as
Latest bibliographic data on file with the International Bureau