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1. WO2020063413 - CHIP AND CHIP TEST SYSTEM

Publication Number WO/2020/063413
Publication Date 02.04.2020
International Application No. PCT/CN2019/106358
International Filing Date 18.09.2019
IPC
G01R 31/28 2006.01
GPHYSICS
01MEASURING; TESTING
RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
31Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
28Testing of electronic circuits, e.g. by signal tracer
G11C 29/00 2006.01
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
29Checking stores for correct operation; Testing stores during standby or offline operation
CPC
G01R 31/28
GPHYSICS
01MEASURING; TESTING
RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
31Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
28Testing of electronic circuits, e.g. by signal tracer
G11C 2029/5602
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
29Checking stores for correct operation ; ; Subsequent repair; Testing stores during standby or offline operation
56External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
5602Interface to device under test
G11C 29/023
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
29Checking stores for correct operation ; ; Subsequent repair; Testing stores during standby or offline operation
02Detection or location of defective auxiliary circuits, e.g. defective refresh counters
023in clock generator or timing circuitry
G11C 29/14
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
29Checking stores for correct operation ; ; Subsequent repair; Testing stores during standby or offline operation
04Detection or location of defective memory elements ; , e.g. cell constructio details, timing of test signals
08Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
12Built-in arrangements for testing, e.g. built-in self testing [BIST] ; or interconnection details
14Implementation of control logic, e.g. test mode decoders
G11C 29/48
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
29Checking stores for correct operation ; ; Subsequent repair; Testing stores during standby or offline operation
04Detection or location of defective memory elements ; , e.g. cell constructio details, timing of test signals
08Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
48Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths
G11C 29/56012
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
29Checking stores for correct operation ; ; Subsequent repair; Testing stores during standby or offline operation
56External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
56012Timing aspects, clock generation, synchronisation
Applicants
  • CHANGXIN MEMORY TECHNOLOGIES, INC. [CN]/[CN]
Inventors
  • NING, Shu-Liang
Agents
  • SHANGHAI SAVVY INTELLECTUAL PROPERTY AGENCY
Priority Data
201811137174.728.09.2018CN
201821631053.328.09.2018CN
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) CHIP AND CHIP TEST SYSTEM
(FR) PUCE ET SYSTÈME D’ESSAI DE PUCE
Abstract
(EN)
A chip (1) and a chip test system,the chip (1) includes a decoding module (11) and a test mode control module (12), and decodes an input signal to determine whether the input signal is a pre-activation signal or not. If the input signal is decoded into a pre-activation signal, then the chip (1) will respond to a subsequent test signal; otherwise, the chip (1) will not respond to any subsequent test signal. By configuring a pre-acti-vation signal, the number of chips (1) to be simultaneously connected to and individ-ually tested by the test equipment (2) can be increased, without the need to occupy more input/output (I/O) interfaces.
(FR)
La présente invention concerne une puce (1) et un système d’essai de puce, la puce (1) comprenant un module de décodage (11) et un module de commande de mode d’essai (12), et décodant un signal d’entrée pour déterminer si le signal d’entrée est un signal de préactivation ou non. Si le signal d’entrée est décodé en signal de préactivation, alors la puce (1) répondra à un signal d’essai ultérieur ; sinon, la puce (1) ne répondra pas à un signal d’essai ultérieur quelconque. Par configuration d’un signal de préactivation, le nombre de puces (1) devant être simultanément connectées à l’équipement d’essai (2) et individuellement testées par celui-ci peut être augmenté, sans nécessiter d’occuper plus d’interfaces d’entrée/sortie (E/S).
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