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1. WO2020062829 - FIN-TYPE SUPER-JUNCTION POWER SEMICONDUCTOR TRANSISTOR AND PREPARATION METHOD THEREFOR

Publication Number WO/2020/062829
Publication Date 02.04.2020
International Application No. PCT/CN2019/081807
International Filing Date 08.04.2019
IPC
H01L 29/78 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66Types of semiconductor device
68controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76Unipolar devices
772Field-effect transistors
78with field effect produced by an insulated gate
H01L 29/423 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
40Electrodes
41characterised by their shape, relative sizes or dispositions
423not carrying the current to be rectified, amplified or switched
H01L 21/336 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18the devices having semiconductor bodies comprising elements of group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
334Multistep processes for the manufacture of devices of the unipolar type
335Field-effect transistors
336with an insulated gate
CPC
H01L 29/42364
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; ; Multistep manufacturing processes therefor
40Electrodes ; ; Multistep manufacturing processes therefor
41characterised by their shape, relative sizes or dispositions
423not carrying the current to be rectified, amplified or switched
42312Gate electrodes for field effect devices
42316for field-effect transistors
4232with insulated gate
42364characterised by the insulating layer, e.g. thickness or uniformity
H01L 29/66795
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; ; Multistep manufacturing processes therefor
66Types of semiconductor device ; ; Multistep manufacturing processes therefor
66007Multistep manufacturing processes
66075of devices having semiconductor bodies comprising group 14 or group 13/15 materials
66227the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
66409Unipolar field-effect transistors
66477with an insulated gate, i.e. MISFET
66787with a gate at the side of the channel
66795with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
H01L 29/785
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; ; Multistep manufacturing processes therefor
66Types of semiconductor device ; ; Multistep manufacturing processes therefor
68controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
76Unipolar devices ; , e.g. field effect transistors
772Field effect transistors
78with field effect produced by an insulated gate
785having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Applicants
  • 东南大学 SOUTHEAST UNIVERSITY [CN]/[CN]
Inventors
  • 孙伟锋 SUN, Weifeng
  • 刘斯扬 LIU, Siyang
  • 童鑫 TONG, Xin
  • 钊雪会 ZHAO, Xuehui
  • 徐浩 XU, Hao
  • 陆生礼 LU, Shengli
  • 时龙兴 SHI, Longxing
Agents
  • 南京瑞弘专利商标事务所(普通合伙) NANJING RUIHONG PATENT & TRADEMARK AGENCY (ORDINARY PARTNERSHIP)
Priority Data
201811155824.029.09.2018CN
Publication Language Chinese (ZH)
Filing Language Chinese (ZH)
Designated States
Title
(EN) FIN-TYPE SUPER-JUNCTION POWER SEMICONDUCTOR TRANSISTOR AND PREPARATION METHOD THEREFOR
(FR) TRANSISTOR À SEMI-CONDUCTEURS DE PUISSANCE À SUPER-JONCTION DE TYPE À AILETTES ET SON PROCÉDÉ DE PRÉPARATION
(ZH) 一种鳍式超结功率半导体晶体管及其制备方法
Abstract
(EN)
A fin-type super-junction power semiconductor transistor and a preparation method therefor. The fin-type super-junction power semiconductor transistor comprises: an N-type substrate (1); an N-type epitaxial layer (2) provided on the N-type substrate (1); a columnar first P-type body region (3) and a second P-type body region (4) provided at two sides inside the N-type epitaxial layer (2); a first N-type heavily doped source region (6) provided on a surface of the second P-type body region (4); a third P-type body region (5) provided on the top of the N-type epitaxial layer (2); second N-type heavily doped source regions (7) respectively provided on a surface of the third P-type body region (5) at both ends; gate polysilicon (10) provided at two sides of the third P-type body region (5); and a second P-type body region (4) covering the bottom of the gate polysilicon (10). The columnar first P-type body region (3), the second P-type body region (4), and part of the N-type epitaxial layer (2) are lower than a lower surface of the third P-type body region (5). The first N-type heavily doped source region (6) on the surface of the second P-type body region (4) terminates at an outer boundary of a gate oxide layer (9). The first N-type heavily doped source region (6) and the second P-type body region (4) synchronously protrude toward the outside of the transistor and are in the shape of a pulse, so as to further reduce on-resistance and reduce EMI noise of devices while ensuring breakdown voltages.
(FR)
La présente invention concerne un transistor à semi-conducteurs de puissance à super-jonction de type à ailettes et son procédé de préparation. Le transistor à semi-conducteurs de puissance à super-jonction de type à ailettes comprend : un substrat de type N (1); une couche épitaxiale de type N (2) disposée sur le substrat de type N (1); une première région de corps de type P en colonne (3) et une deuxième région de corps de type P (4) disposée sur deux côtés à l'intérieur de la couche épitaxiale de type N (2); une première région de source fortement dopée de type N (6) disposée sur une surface de la seconde région de corps de type P (4); une troisième région de corps de type P (5) disposée sur la partie supérieure de la couche épitaxiale de type N (2); des secondes régions de source fortement dopées de type N (7) disposées respectivement sur une surface de la troisième région de corps de type P (5) aux deux extrémités; du polysilicium de grille (10) disposé sur deux côtés de la troisième région de corps de type P (5); et une deuxième région de corps de type P (4) recouvrant la partie supérieure du polysilicium de grille (10). La première région de corps de type P en colonne (3), la deuxième région de corps de type P (4) et une partie de la couche épitaxiale de type N (2) sont plus basses qu'une surface inférieure de la troisième région de corps de type P (5). La première région de source fortement dopée de type N (6) sur la surface de la deuxième région de corps de type P (4) se termine au niveau d'une limite externe d'une couche d'oxyde de grille (9). La première région de source fortement dopée de type N (6) et la deuxième région de corps de type P (4) font saillie de manière synchrone vers l'extérieur du transistor et se présentent sous la forme d'une impulsion, de façon à réduire davantage la résistance à l'état passant et à réduire le bruit EMI des dispositifs tout en assurant des tensions de claquage.
(ZH)
一种鳍式超结功率半导体晶体管及其制备方法,包括N型衬底(1),在N型衬底(1)上设有N型外延层(2),在N型外延层(2)内的两侧设有柱状第一P型体区(3)和第二P型体区(4),在第二P型体区(4)表面设有第一N型重掺杂源区(6),在N型外延层(2)顶部设有第三P型体区(5),该区表面两端设有第二N型重掺杂源区(7),第三P型体区(5)两侧分别设有栅极多晶硅(10),且栅极多晶硅(10)下方覆盖第二P型体区(4),柱状第一P型体区(3)、第二P型体区(4)及部分N型外延层(2)低于第三P型体区(5)下表面。第二P型体区(4)表面的第一N型重掺杂源区(6)止于栅氧化层(9)的外侧边界,第一N型重掺杂源区(6)与第二P型体区(4)向晶体管外侧同步外凸并呈脉冲形状,从而在保证击穿电压的前提下进一步降低导通电阻,降低器件EMI噪声。
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