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1. WO2020021551 - SYSTEM FOR IMPLEMENTING SHARED LOCK FREE MEMORY IMPLEMENTING COMPOSITE ASSIGNMENT

Publication Number WO/2020/021551
Publication Date 30.01.2020
International Application No. PCT/IL2019/050842
International Filing Date 24.07.2019
IPC
G06F 13/16 2006.1
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
13Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
14Handling requests for interconnection or transfer
16for access to memory bus
H01L 27/108 2006.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
10including a plurality of individual components in a repetitive configuration
105including field-effect components
108Dynamic random access memory structures
G11C 13/00 2006.1
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
13Digital stores characterised by the use of storage elements not covered by groups G11C11/, G11C23/, or G11C25/173
CPC
G06F 11/0724
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
11Error detection; Error correction; Monitoring
07Responding to the occurrence of a fault, e.g. fault tolerance
0703Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
0706the processing taking place on a specific hardware platform or in a specific software environment
0721within a central processing unit [CPU]
0724in a multiprocessor or a multi-core unit
G06F 12/00
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
12Accessing, addressing or allocating within memory systems or architectures
G06F 13/38
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
13Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
38Information transfer, e.g. on bus
G06F 9/46
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
46Multiprogramming arrangements
G06F 9/466
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
46Multiprogramming arrangements
466Transaction processing
G11C 11/4076
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21using electric elements
34using semiconductor devices
40using transistors
401forming cells needing refreshing or charge regeneration, i.e. dynamic cells
4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
407for memory cells of the field-effect type
4076Timing circuits
Applicants
  • JERUSALEM COLLEGE OF TECHNOLOGY [IL]/[IL]
Inventors
  • MIZRAHI, Shimon
  • YEHEZKAEL, Raphael Berakhael
  • ATTIA, Ruben
  • LAX, Erez
  • BERLOWITZ, Devora
  • GOLDSTEIN, Moshe
  • DAYAN, David
Agents
  • HADARI, Gilad
Priority Data
62/702,37324.07.2018US
Publication Language English (en)
Filing Language English (EN)
Designated States
Title
(EN) SYSTEM FOR IMPLEMENTING SHARED LOCK FREE MEMORY IMPLEMENTING COMPOSITE ASSIGNMENT
(FR) SYSTÈME DE MISE EN ŒUVRE D'UNE MÉMOIRE PARTAGÉE SANS VERROUILLAGE METTANT EN ŒUVRE UNE ATTRIBUTION COMPOSITE
Abstract
(EN) It is an object of the disclosed technique to provide a novel method and system for shared concurrent access to a memory cell. In accordance with the disclosed technique, there is thus provided a system for shared concurrent access to a memory cell, which includes at least one shared memory cell, an evaluator and a plurality of processing agents coupled to the input of the evaluator. The evaluator is further coupled with the at least one memory cell. The evaluator is configured to evaluate an expression for performing multiple concurrent composite assignments on the at least one shared memory cell. The evaluator further allows each of the plurality of processing agents to perform concurrent composite assignments on the at least one shared memory cell. The composite assignments do not include a read operation of the at least one shared memory cell by the plurality of processing agents.
(FR) La présente invention vise à fournir un nouveau procédé et un système d'accès simultané partagé à une cellule de mémoire. La présente invention concerne un système d'accès simultané partagé à une cellule de mémoire, lequel comprend au moins une cellule de mémoire partagée, un évaluateur et une pluralité d'agents de traitement couplés à l'entrée de l'évaluateur. L'évaluateur est en outre couplé à ladite au moins une cellule de mémoire. L'évaluateur est conçu pour évaluer une expression pour réaliser de multiples attributions composites simultanées sur ladite au moins une cellule de mémoire partagée. L'évaluateur permet en outre à l'agent de traitement respectif de la pluralité d'agents de traitement d'effectuer des attributions composites simultanées sur ladite au moins une cellule de mémoire partagée. Les attributions composites ne comprennent pas d'opération de lecture de ladite au moins une cellule de mémoire partagée par la pluralité d'agents de traitement.
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