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1. WO2020006831 - ARRAY SUBSTRATE AND FABRICATION METHOD THEREFOR

Publication Number WO/2020/006831
Publication Date 09.01.2020
International Application No. PCT/CN2018/101962
International Filing Date 23.08.2018
IPC
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
786
Thin-film transistors
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
12
the substrate being other than a semiconductor body, e.g. an insulating body
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
334
Multistep processes for the manufacture of devices of the unipolar type
335
Field-effect transistors
336
with an insulated gate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
H01L 29/786 (2006.01)
H01L 27/12 (2006.01)
H01L 21/336 (2006.01)
H01L 21/77 (2017.01)
CPC
H01L 2227/323
H01L 27/3244
Applicants
  • 武汉华星光电半导体显示技术有限公司 WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD. [CN/CN]; 中国湖北省武汉市 东湖新技术开发区高新大道666号光谷生物创新园C5栋305室 305 Room, Building C5, Biolake of Optics Valley, No.666 Gaoxin Avenue, Wuhan East Lake High-tech Development Zone, Wuhan, Hubei 430079, CN
Inventors
  • 陈彩琴 CHEN, Caiqin; CN
  • 明星 MING, Xing; CN
Agents
  • 深圳翼盛智成知识产权事务所(普通合伙) ESSEN PATENT&TRADEMARK AGENCY; 中国广东省深圳市 福田区深南大道6021号喜年中心A座1709-1711 Room 1709-1711 Block A, Hailrun Complex, NO.6021 Shennan Blvd, Futian District ShenZhen, Guangdong 518040, CN
Priority Data
201810726708.304.07.2018CN
Publication Language Chinese (ZH)
Filing Language Chinese (ZH)
Designated States
Title
(EN) ARRAY SUBSTRATE AND FABRICATION METHOD THEREFOR
(FR) SUBSTRAT DE MATRICE ET SON PROCÉDÉ DE FABRICATION
(ZH) 一种阵列基板及其制作方法
Abstract
(EN)
Provided in the present invention is a method for fabricating an array substrate: forming a first photoresist pattern on a buffer layer of a non-display region, removing a buffer layer not covered by the first photoresist pattern so as to form first vias on the non-display region, and forming second vias on the foundation of the first vias, wherein the second vias and the first vias are connected. By means of forming first vias on a non-display region and forming second vias on the foundation of the first vias, the completeness of a film layer may be ensured, thus improving product yield.
(FR)
La présente invention concerne un procédé destiné à fabriquer un substrat de matrice consistant : à former un premier motif photorésistant sur une couche tampon d'une zone de non-affichage, à retirer une couche tampon non recouverte par le premier motif photorésistant afin de former des premières interconnexions sur la zone de non-affichage, et à former des deuxièmes interconnexions sur la fondation des premières interconnexions, les premières interconnexions et les deuxièmes interconnexions étant connectées. En formant de premières interconnexions sur une zone de non-affichage et en formant de deuxièmes interconnexions sur la fondation des premières interconnexions, le caractère complet d'une couche de pellicule peut être assuré, améliorant ainsi le rendement de produit.
(ZH)
本发明提供的阵列基板的制作方法,在非显示区的缓冲层上形成第一光刻胶图案,去除未被第一光刻胶图案覆盖的缓冲层,以在非显示区上形成第一过孔,在第一过孔的基础上形成第二过孔,其中,第二过孔与第一过孔相连接。通过在非显示区形成第一过孔,并在第一过孔的基础上形成第二过孔,可以保证膜层的完整性,提高了产品良率。
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