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1. WO2020006464 - HOST SIDE CACHING SECURITY FOR FLASH MEMORY

Publication Number WO/2020/006464
Publication Date 02.01.2020
International Application No. PCT/US2019/039902
International Filing Date 28.06.2019
IPC
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
12
Accessing, addressing or allocating within memory systems or architectures
14
Protection against unauthorised use of memory
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
12
Accessing, addressing or allocating within memory systems or architectures
02
Addressing or allocation; Relocation
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
21
Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
70
Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
78
to assure secure storage of data
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
3
Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
06
Digital input from, or digital output to, record carriers
G06F 12/14 (2006.01)
G06F 12/02 (2006.01)
G06F 21/78 (2013.01)
G06F 3/06 (2006.01)
CPC
G06F 12/1408
G06F 21/602
G06F 2212/1052
Applicants
  • MICRON TECHNOLOGY, INC. [US/US]; 8000 So. Federal Way Boise, Idaho 83716-9632, US
Inventors
  • SZUBBOCSEV, Zoltan; US
  • TROIA, Alberto; DE
  • TIZIANI, Federico; DE
Agents
  • PERDOK, Monique, M.; US
  • ARORA, Suneel / U.S. Reg. No. 42,267; US
  • BEEKMAN, Marvin / U.S. Reg. No. 38,377; US
  • BLACK, David W. / U.S. Reg. No. 42,331; US
  • LANG, Roger / U.S. Reg. No. 58,829; US
  • SCHEER, Bradley W. / U.S. Reg. No. 47,059; US
Priority Data
16/023,24729.06.2018US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) HOST SIDE CACHING SECURITY FOR FLASH MEMORY
(FR) SÉCURITÉ DE MISE EN CACHE CÔTÉ HÔTE POUR MÉMOIRE FLASH
Abstract
(EN)
Various examples are directed to systems and methods for managing a memory system. The memory system may generate a first encrypted physical address using a first clear physical address. The memory system may generate a first encrypted logical-to-physical (L2P) pointer indicating the first logical address and a first encrypted physical address. The memory system may send the first encrypted L2P pointer to a host device for storage at a host memory.
(FR)
Selon divers exemples, l'invention concerne des systèmes et des procédés de gestion d'un système de mémoire. Le système de mémoire peut générer une première adresse physique (PA) chiffrée à l'aide d'une première adresse physique en clair. Le système de mémoire peut générer un premier pointeur logique-physique (L2P) chiffré indiquant une première adresse logique (LA) et la première adresse physique chiffrée. Le système de mémoire peut envoyer le premier pointeur L2P chiffré à un dispositif hôte en vue de son stockage au niveau d'une mémoire hôte.
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