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1. WO2020005543 - SEMICONDUCTOR DEVICES WITH THROUGH SILICON VIAS AND PACKAGE-LEVEL CONFIGURABILITY

Publication Number WO/2020/005543
Publication Date 02.01.2020
International Application No. PCT/US2019/036696
International Filing Date 12.06.2019
IPC
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25
Assemblies consisting of a plurality of individual semiconductor or other solid state devices
03
all the devices being of a type provided for in the same subgroup of groups H01L27/-H01L51/128
04
the devices not having separate containers
07
the devices being of a type provided for in group H01L29/78
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25
Assemblies consisting of a plurality of individual semiconductor or other solid state devices
03
all the devices being of a type provided for in the same subgroup of groups H01L27/-H01L51/128
04
the devices not having separate containers
065
the devices being of a type provided for in group H01L27/78
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
48
Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
488
consisting of soldered or bonded constructions
498
Leads on insulating substrates
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
58
Structural electrical arrangements for semiconductor devices not otherwise provided for
60
Protection against electrostatic charges or discharges, e.g. Faraday shields
H01L 25/07 (2006.01)
H01L 25/065 (2006.01)
H01L 23/498 (2006.01)
H01L 23/00 (2006.01)
H01L 23/60 (2006.01)
CPC
H01L 2224/0401
H01L 2224/05009
H01L 2224/05076
H01L 2224/05078
H01L 2224/0508
H01L 2224/05085
Applicants
  • MICRON TECHNOLOGY, INC. [US/US]; 8000 S. Federal Way, P.O. Box 6 Boise, ID 83707-0006, US
Inventors
  • DUESMAN, Kevin, G.; US
  • DAVIS, James, E.; US
  • BOYER, Warren, L.; US
Agents
  • PARKER, Paul, T.; US
  • ALLBEE, Dannon; US
  • DUNHAM, Nicole, S.; US
  • ARNETT, Stephen, E.; US
  • COX, Tyler, S.; US
Priority Data
16/020,79227.06.2018US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) SEMICONDUCTOR DEVICES WITH THROUGH SILICON VIAS AND PACKAGE-LEVEL CONFIGURABILITY
(FR) DISPOSITIFS À SEMI-CONDUCTEUR AYANT DES TROUS D'INTERCONNEXION TRAVERSANTS LE SILICIUM ET CONFIGURABILITÉ DE NIVEAU DE BOÎTIER
Abstract
(EN)
A semiconductor device assembly includes a substrate and a die coupled to the substrate, the die including a first contact pad electrically coupled to a first circuit on the die including an active circuit element, a first TSV electrically coupling the first contact pad to a first backside contact pad, and a second contact pad electrically coupled to a second circuit including only passive circuit elements. The substrate includes a substrate contact electrically coupled to the first and second contact pads. The assembly can further include a second die including a third contact pad electrically coupled to a third circuit including a second active circuit element, and a fourth contact pad electrically coupled to a fourth circuit on the second die including only passive circuit elements. The substrate contact can be electrically coupled to the third contact pad, but electrically disconnected from the fourth contact pad.
(FR)
L'invention concerne un ensemble dispositif à semi-conducteur comprenant un substrat et une puce couplée au substrat, la puce comprenant un premier plot de contact couplé électriquement à un premier circuit sur la puce comprenant un élément de circuit actif, un premier TSV couplant électriquement le premier plot de contact à un premier plot de contact arrière, et un second plot de contact couplé électriquement à un second circuit comprenant uniquement des éléments de circuit passifs. Le substrat comprend un contact de substrat couplé électriquement aux premier et second plots de contact. L'ensemble peut en outre comprendre une seconde puce comprenant un troisième plot de contact couplé électriquement à un troisième circuit comprenant un second élément de circuit actif, et un quatrième plot de contact couplé électriquement à un quatrième circuit sur la seconde puce comprenant uniquement des éléments de circuit passifs. Le contact de substra peut être couplé électriquement au troisième plot de contact, mais déconnecté électriquement du quatrième plot de contact.
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