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1. WO2020005435 - INTEGRATED MAGNETIC CORE INDUCTORS ON GLASS CORE SUBSTRATES

Publication Number WO/2020/005435
Publication Date 02.01.2020
International Application No. PCT/US2019/034113
International Filing Date 28.05.2019
IPC
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
58
Structural electrical arrangements for semiconductor devices not otherwise provided for
64
Impedance arrangements
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
48
Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
482
consisting of lead-in layers inseparably applied to the semiconductor body
485
consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
52
Arrangements for conducting electric current within the device in operation from one component to another
522
including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
12
Mountings, e.g. non-detachable insulating substrates
14
characterised by the material or its electrical properties
15
Ceramic or glass substrates
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
50
Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/06-H01L21/326162
56
Encapsulations, e.g. encapsulating layers, coatings
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25
Assemblies consisting of a plurality of individual semiconductor or other solid state devices
03
all the devices being of a type provided for in the same subgroup of groups H01L27/-H01L51/128
04
the devices not having separate containers
065
the devices being of a type provided for in group H01L27/78
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25
Assemblies consisting of a plurality of individual semiconductor or other solid state devices
03
all the devices being of a type provided for in the same subgroup of groups H01L27/-H01L51/128
04
the devices not having separate containers
07
the devices being of a type provided for in group H01L29/78
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25
Assemblies consisting of a plurality of individual semiconductor or other solid state devices
16
the devices being of types provided for in two or more different main groups of groups H01L27/-H01L51/139
H01L 23/64 (2006.01)
H01L 23/485 (2006.01)
H01L 23/522 (2006.01)
H01L 23/15 (2006.01)
H01L 21/56 (2006.01)
H01L 25/065 (2006.01)
CPC
H01F 17/0006
H01F 17/06
H01F 2017/0066
H01F 2017/065
H01F 27/24
H01F 27/2804
Applicants
  • INTEL CORPORATION [US/US]; 2200 Mission College Blvd. Santa Clara, California 95054, US
Inventors
  • BHARATH, Krishna; US
  • ELSHERBINI, Adel; US
Agents
  • GILBERT, Scott Evan; US
Priority Data
16/024,59329.06.2018US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) INTEGRATED MAGNETIC CORE INDUCTORS ON GLASS CORE SUBSTRATES
(FR) BOBINES D'INDUCTION À NOYAU MAGNÉTIQUE INTÉGRÉES SUR DES SUBSTRATS DE NOYAU EN VERRE
Abstract
(EN)
A microelectronics package comprising a package core and an inductor over the package core. The inductor comprises a dielectric over the package core. The dielectric comprises a curved surface opposite the package core. At least one conductive trace is adjacent to the package core. The at least one conductive trace is at least partially embedded within the dielectric and extends over the package core. A magnetic core cladding is over the dielectric layer and at least partially surrounding the conductive trace.
(FR)
L'invention concerne un boîtier micro-électronique comprenant un noyau de boîtier et une bobine d'induction sur le noyau de boîtier. La bobine d'induction comprend un diélectrique sur le noyau de boîtier. Le diélectrique comprend une surface incurvée opposée au noyau de boîtier. Au moins une trace conductrice est adjacente au noyau de boîtier. Ladite trace conductrice est au moins partiellement incorporée dans le diélectrique et s'étend sur le noyau de boîtier. Une gaine de noyau magnétique est située sur la couche diélectrique et entoure au moins partiellement la trace conductrice.
Latest bibliographic data on file with the International Bureau