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1. WO2020005415 - QUANTUM DOT DEVICES WITH MULTIPLE DIELECTRICS AROUND FINS

Publication Number WO/2020/005415
Publication Date 02.01.2020
International Application No. PCT/US2019/033298
International Filing Date 21.05.2019
IPC
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
778
with two-dimensional charge carrier gas channel, e.g. HEMT
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
02
Semiconductor bodies
12
characterised by the materials of which they are formed
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
02
Semiconductor bodies
06
characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78
with subsequent division of the substrate into plural individual devices
82
to produce devices, e.g. integrated circuits, each consisting of a plurality of components
822
the substrate being a semiconductor, using silicon technology
8232
Field-effect technology
8234
MIS technology
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
40
Electrodes
43
characterised by the materials of which they are formed
49
Metal-insulator semiconductor electrodes
51
Insulating materials associated therewith
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04
the substrate being a semiconductor body
08
including only semiconductor components of a single kind
085
including field-effect components only
088
the components being field-effect transistors with insulated gate
H01L 29/778 (2006.01)
H01L 29/12 (2006.01)
H01L 29/06 (2006.01)
H01L 29/66 (2006.01)
H01L 21/8234 (2006.01)
H01L 29/51 (2006.01)
CPC
B82Y 10/00
G06N 10/00
H01L 21/0217
H01L 21/02266
H01L 21/3081
H01L 21/3086
Applicants
  • INTEL CORPORATION [US/US]; 2200 Mission College Boulevard Santa Clara, California 95054-1549, US
Inventors
  • GEORGE, Hubert C.; US
  • MICHALAK, David J.; US
  • PILLARISETTY, Ravi; US
  • LAMPERT, Lester; US
  • CLARKE, James S.; US
  • YOSCOVITS, Zachary R.; US
  • THOMAS, Nicole K.; US
  • CAUDILLO, Roman; US
  • SINGH, Kanwaljit; NL
  • ROBERTS, Jeanette M.; US
Agents
  • ZAGER, Laura A.; US
Priority Data
16/017,03125.06.2018US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) QUANTUM DOT DEVICES WITH MULTIPLE DIELECTRICS AROUND FINS
(FR) DISPOSITIFS À POINTS QUANTIQUES DOTÉS DE MULTIPLES DIÉLECTRIQUES AUTOUR D'AILETTES
Abstract
(EN)
Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a base; a fin extending away from the base, wherein the fin includes a quantum well layer; a first dielectric material around a bottom portion of the fin; and a second dielectric material around a top portion of the fin, wherein the second dielectric material is different from the first dielectric material.
(FR)
La présente invention concerne des dispositifs à points quantiques, ainsi que des dispositifs informatiques et des procédés associés. Par exemple, selon certains modes de réalisation, un dispositif à points quantiques peut comprendre : une base ; une ailette s'étendant à l'opposé de la base, l'ailette comprenant une couche de puits quantique ; un premier matériau diélectrique autour d'une partie inférieure de l'ailette ; et un second matériau diélectrique autour d'une partie supérieure de l'ailette, le second matériau diélectrique étant différent du premier matériau diélectrique.
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