Processing

Please wait...

Settings

Settings

1. WO2020005392 - HYBRID FAN-OUT ARCHITECTURE WITH EMIB AND GLASS CORE FOR HETEROGENEOUS DIE INTEGRATION APPLICATIONS

Publication Number WO/2020/005392
Publication Date 02.01.2020
International Application No. PCT/US2019/031182
International Filing Date 07.05.2019
IPC
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
48
Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
482
consisting of lead-in layers inseparably applied to the semiconductor body
485
consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
48
Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
12
Mountings, e.g. non-detachable insulating substrates
14
characterised by the material or its electrical properties
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
12
Mountings, e.g. non-detachable insulating substrates
14
characterised by the material or its electrical properties
15
Ceramic or glass substrates
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
52
Arrangements for conducting electric current within the device in operation from one component to another
538
the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
34
Arrangements for cooling, heating, ventilating or temperature compensation
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
50
Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/06-H01L21/326162
56
Encapsulations, e.g. encapsulating layers, coatings
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
H01L 23/485 (2006.01)
H01L 23/48 (2006.01)
H01L 23/14 (2006.01)
H01L 23/15 (2006.01)
H01L 23/538 (2006.01)
H01L 23/34 (2006.01)
CPC
H01L 21/4853
H01L 21/486
H01L 21/565
H01L 21/6835
H01L 2221/68345
H01L 2221/68359
Applicants
  • INTEL CORPORATION [US/US]; 2200 Mission College Boulevard Santa Clara, California 95054, US
Inventors
  • PIETAMBARAM, Srinivas; US
  • MANEPALLI, Rahul; US
  • DUAN, Gang; US
Agents
  • BERNADICOU, Michael A.; US
  • AUYEUNG, Al; US
  • BLAIR, Steven R.; US
  • BLANK, Eric S.; US
  • BRASK, Justin K.; US
  • COFIELD, Michael A.; US
  • DANSKIN, Timothy A.; US
  • GARTHWAITE, Martin S.; US
  • MAKI, Nathan R.; US
  • PARKER, Wesley E.; US
  • PUGH, Joseph A.; US
  • RASKIN, Vladimir; US
  • STRAUSS, Ryan N.; US
  • WANG, Yuke; US
  • YATES, Steven D.; US
Priority Data
16/024,70729.06.2018US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) HYBRID FAN-OUT ARCHITECTURE WITH EMIB AND GLASS CORE FOR HETEROGENEOUS DIE INTEGRATION APPLICATIONS
(FR) ARCHITECTURE DE SORTANCE HYBRIDE DOTÉE D'UN EMIB ET D'UNE ÂME EN VERRE POUR DES APPLICATIONS D'INTÉGRATION DE PUCE HÉTÉROGÈNES
Abstract
(EN)
Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, a microelectronic device package may include a redistribution layer (RDL) and an interposer over the RDL. In an embodiment, a glass core may be formed over the RDL and surround the interposer. In an embodiment, the microelectronic device package may further comprise a plurality of dies over the interposer. In an embodiment, the plurality of dies are communicatively coupled with the interposer.
(FR)
Des modes de réalisation de l'invention comprennent des boîtiers électroniques et des procédés de formation de tels boîtiers. Selon un mode de réalisation, un boîtier de dispositif microélectronique peut comprendre une couche de redistribution (RDL) et un interposeur sur la RDL. Selon un mode de réalisation, une âme en verre peut être formée sur la RDL et entourer l'interposeur. Selon un mode de réalisation, le boîtier de dispositif microélectronique peut en outre comprendre une pluralité de puces sur l'interposeur. Selon un mode de réalisation, la pluralité de puces sont couplées en communication avec l'interposeur.
Latest bibliographic data on file with the International Bureau