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1. WO2020005389 - POST ETCH DEFLUORINATION PROCESS

Publication Number WO/2020/005389
Publication Date 02.01.2020
International Application No. PCT/US2019/031001
International Filing Date 07.05.2019
IPC
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30
Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
302
to change the physical characteristics of their surfaces, or to change their shape, e.g. etching, polishing, cutting
306
Chemical or electrical treatment, e.g. electrolytic etching
3065
Plasma etching; Reactive-ion etching
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
027
Making masks on semiconductor bodies for further photolithographic processing, not provided for in group H01L21/18 or H01L21/34165
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30
Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
31
to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After-treatment of these layers; Selection of materials for these layers
3105
After-treatment
311
Etching the insulating layers
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30
Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
31
to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After-treatment of these layers; Selection of materials for these layers
3205
Deposition of non-insulating-, e.g. conductive- or resistive-, layers, on insulating layers; After-treatment of these layers
321
After-treatment
3213
Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
67
Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
J
ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
37
Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
32
Gas-filled discharge tubes
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30
Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
324
Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
H01L 21/3065 (2006.01)
H01L 21/027 (2006.01)
H01L 21/311 (2006.01)
H01L 21/3213 (2006.01)
H01L 21/67 (2006.01)
H01J 37/32 (2006.01)
CPC
H01L 21/0206
H01L 21/02071
H01L 21/02076
H01L 21/3065
H01L 21/311
H01L 21/31138
Applicants
  • MATTSON TECHNOLOGY, INC. [US/US]; 47131 Bayside Parkway Fremont, California 94538, US
  • BEIJING E-TOWN SEMICONDUCTOR TECHNOLOGY, CO., LTD [CN/CN]; No. 8 Building, No. 28 Jinghai Er Rd. Economic and Technical Development Zone Beijing 100176, CN
Inventors
  • VANIAPURA, Vijay Matthew; US
  • GRAMADA, Andrei; US
Agents
  • WORKMAN, J. Parks; US
Priority Data
62/689,47525.06.2018US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) POST ETCH DEFLUORINATION PROCESS
(FR) PROCÉDÉ DE DÉFLUORATION POST-GRAVURE
Abstract
(EN)
Defluorination processes for removing fluorine residuals from a workpiece such as a semiconductor wafer are provided. In one example implementation, a method for processing a workpiece can include supporting a workpiece on a workpiece support. The workpiece can have a photoresist layer. The workpiece can have one or more fluorine residuals on a surface of the workpiece. The method can include performing a defluorination process on the workpiece at least in part using a plasma generated from a first process gas. The first process gas can include a hydrogen gas. Subsequent to performing the defluorination process, the method can include performing a plasma strip process on the workpiece to at least partially remove a photoresist layer from the workpiece.
(FR)
L'invention concerne des procédés de défluoration pour éliminer des résidus de fluor d'une pièce telle qu'une tranche de semi-conducteur. Dans un exemple de mode de réalisation, un procédé de traitement d'une pièce peut comprendre le support d'une pièce sur un support de pièce. La pièce peut avoir une couche de résine photosensible. La pièce peut avoir un ou plusieurs résidus de fluor sur une surface de la pièce. Le procédé peut comprendre la réalisation d'un processus de défluoration sur la pièce au moins en partie à l'aide d'un plasma généré à partir d'un premier gaz de traitement. Le premier gaz de traitement peut comprendre un gaz hydrogène. À la suite de la réalisation du procédé de défluoration, le procédé peut comprendre la réalisation d'un traitement de bande de plasma sur la pièce pour éliminer au moins partiellement une couche de résine photosensible de la pièce.
Latest bibliographic data on file with the International Bureau