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1. (WO2020005324) CONTENT ADDRESSABLE MEMORY USING THRESHOLD-ADJUSTABLE VERTICAL TRANSISTORS AND METHODS OF FORMING THE SAME
Latest bibliographic data on file with the International BureauSubmit observation

Pub. No.: WO/2020/005324 International Application No.: PCT/US2019/017079
Publication Date: 02.01.2020 International Filing Date: 07.02.2019
IPC:
G11C 15/04 (2006.01) ,G11C 11/22 (2006.01) ,H01L 29/78 (2006.01)
G PHYSICS
11
INFORMATION STORAGE
C
STATIC STORES
15
Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
04
using semiconductor elements
G PHYSICS
11
INFORMATION STORAGE
C
STATIC STORES
11
Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21
using electric elements
22
using ferroelectric elements
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
Applicants:
SANDISK TECHNOLOGIES LLC [US/US]; 5080 Spectrum Drive, Suite 1050W Addison, Texas 75001, US
Inventors:
PETTI, Christopher J.; US
Agent:
MAGEN, Burt; US
Priority Data:
16/022,95229.06.2018US
Title (EN) CONTENT ADDRESSABLE MEMORY USING THRESHOLD-ADJUSTABLE VERTICAL TRANSISTORS AND METHODS OF FORMING THE SAME
(FR) MÉMOIRE ADRESSABLE PAR CONTENU UTILISANT DES TRANSISTORS VERTICAUX À SEUIL AJUSTABLE ET PROCÉDÉS DE FORMATION DE CELLE-CI
Abstract:
(EN) A content addressable memory cell array is provided that includes a plurality of match lines in parallel along a first axis, a plurality of ground lines in parallel along a first axis, a plurality of search lines disposed in parallel substantially perpendicular to the first axis, and each content addressable memory element disposed between a corresponding one of the match lines and a corresponding one of the ground lines, and each coupled to a corresponding one of the search lines, wherein a content addressable memory element comprises a vertical transistor comprising a gate oxide comprising a ferroelectric material.
(FR) L'invention concerne un réseau de cellules de mémoire adressable par contenu qui comprend une pluralité de lignes de correspondance en parallèle le long d'un premier axe, une pluralité de lignes de masse en parallèle le long d'un premier axe, une pluralité de lignes de recherche disposées en parallèle sensiblement perpendiculairement au premier axe, et chaque élément de mémoire adressable par contenu étant disposé entre une ligne correspondante parmi les lignes de correspondance et une ligne correspondante parmi les lignes de masse, et chacun couplé à une ligne correspondante parmi les lignes de recherche, un élément de mémoire adressable par contenu comprenant un transistor vertical comprenant un oxyde de grille comprenant un matériau ferroélectrique.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)