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1. WO2020005009 - SEMICONDUCTOR DEVICE

Publication Number WO/2020/005009
Publication Date 02.01.2020
International Application No. PCT/KR2019/007884
International Filing Date 28.06.2019
IPC
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
33
Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
48
characterised by the semiconductor body packages
62
Arrangements for conducting electric current to or from the semiconductor body, e.g. leadframe, wire-bond or solder balls
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
33
Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
02
characterised by the semiconductor bodies
20
with a particular shape, e.g. curved or truncated substrate
22
Roughened surfaces, e.g. at the interface between epitaxial layers
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
33
Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
36
characterised by the electrodes
38
with a particular shape
H01L 33/62 (2010.01)
H01L 33/22 (2010.01)
H01L 33/38 (2010.01)
CPC
H01L 33/22
H01L 33/38
H01L 33/62
Applicants
  • 엘지이노텍 주식회사 LG INNOTEK CO., LTD. [KR/KR]; 서울시 강서구 마곡중앙10로 30 30, Magokjungang 10-ro Gangseo-gu Seoul 07796, KR
Inventors
  • 성연준 SUNG, Youn Joon; KR
Agents
  • 특허법인 다나 DANA PATENT LAW FIRM; 서울시 강남구 역삼로3길 11 광성빌딩 신관4~6층 4~6th Floor, New Wing, Gwangsung Bldg. 11, Yeoksam-ro 3-gil Gangnam-gu Seoul 06242, KR
Priority Data
10-2018-007601729.06.2018KR
Publication Language Korean (KO)
Filing Language Korean (KO)
Designated States
Title
(EN) SEMICONDUCTOR DEVICE
(FR) DISPOSITIF SEMI-CONDUCTEUR
(KO) 반도체 소자
Abstract
(EN)
Disclosed in an embodiment is a semiconductor device comprising: a conductive substrate; a semiconductor structure, which is arranged on the conductive substrate, comprises a first conductive type semiconductor layer, a second conductive type semiconductor layer, and an active layer arranged between the first conductive type semiconductor layer and the second conductive type semiconductor layer, and comprises a plurality of recesses which pass through the second conductive type semiconductor layer and the active layer and up to a partial region of the first conductive type semiconductor layer; a first electrode electrically connecting the first conductive type semiconductor layer to the conductive substrate; a second electrode electrically connected to the second conductive type semiconductor layer; and an insulating layer arranged inside the plurality of recesses, wherein the plurality of recesses comprise a first recess extending along the outer surface of the semiconductor structure and a plurality of second recesses arranged on the inner side of the first recess, the first electrode comprises a plurality of protrusion electrodes extending to the inside of the second recess so as to be electrically connected to the first conductive type semiconductor layer, the active layer comprises an inactive area arranged between a side surface of the semiconductor structure and the first recess, and an active area arranged on the inner side of the first recess, and the emission intensity of the inactive area is less than the emission intensity of the active area.
(FR)
Dans un mode de réalisation, l'invention concerne un dispositif semi-conducteur comprenant: un substrat conducteur; une structure semi-conductrice, qui est disposée sur le substrat conducteur, comprend une première couche semi-conductrice de type conducteur, une seconde couche semi-conductrice de type conducteur, et une couche active disposée entre la première couche semi-conductrice de type conducteur et la seconde couche semi-conductrice de type conducteur, et comprend une pluralité d'évidements qui traversent la première couche semi-conductrice de type conducteur et la couche active et remontent jusqu'à une région partielle de la première couche semi-conductrice de type conducteur; une première électrode connectant électriquement la première couche de semi-conducteur de type conducteur au substrat conducteur; une seconde électrode connectée électriquement à la seconde couche semi-conductrice de type conducteur; et une couche isolante disposée à l'intérieur de la pluralité d'évidements, la pluralité d'évidements comprenant un premier évidement s'étendant le long de la surface extérieure de la structure semi-conductrice et une pluralité de seconds évidements agencés sur le côté intérieur du premier évidement, la première électrode comprend une pluralité d'électrodes en saillie s'étendant vers l'intérieur du second évidement de façon à être électriquement connectées à la première couche semi-conductrice de type conducteur, la couche active comprend une zone inactive disposée entre une surface latérale de la structure semi-conductrice et le premier évidement, et une zone active disposée sur le côté intérieur du premier évidement, l'intensité d'émission de la zone inactive étant inférieure à l'intensité d'émission de la zone active.
(KO)
실시 예는, 도전성 기판; 상기 도전성 기판 상에 배치되며, 제1 도전형 반도체층, 제2 도전형 반도체층, 및 상기 제1 도전형 반도체층과 상기 제2 도전형 반도체층 사이에 배치되는 활성층을 포함하고, 상기 제2 도전형 반도체층, 상기 활성층 및 상기 제1 도전형 반도체층의 일부 영역까지 관통하는 복수의 리세스를 포함하는 반도체 구조물; 상기 제1 도전형 반도체층과 상기 도전성 기판을 전기적으로 연결하는 제1 전극; 상기 제2 도전형 반도체층과 전기적으로 연결되는 제2 전극; 및 상기 복수의 리세스 내에 배치되는 절연층을 포함하고, 상기 복수의 리세스는 상기 반도체 구조물의 외측면을 따라 연장되는 제1 리세스 및 상기 제1 리세스의 내측에 배치되는 복수 개의 제2 리세스를 포함하고, 상기 제1 전극은 상기 제2 리세스 내로 연장되어 상기 제1 도전형 반도체층과 전기적으로 연결되는 복수의 돌출 전극을 포함하고, 상기 활성층은 상기 반도체 구조물 측면과 상기 제1 리세스 사이에 배치된 비활성영역, 및 상기 제1 리세스의 내측에 배치된 활성영역을 포함하고, 상기 비활성영역의 발광 강도는 상기 활성영역의 발광 강도보다 작은 반도체 소자를 개시한다.
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