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1. WO2020004065 - SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

Publication Number WO/2020/004065
Publication Date 02.01.2020
International Application No. PCT/JP2019/023520
International Filing Date 13.06.2019
IPC
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
71
Manufacture of specific parts of devices defined in group H01L21/7086
768
Applying interconnections to be used for carrying current between separate components within a device
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78
with subsequent division of the substrate into plural individual devices
82
to produce devices, e.g. integrated circuits, each consisting of a plurality of components
822
the substrate being a semiconductor, using silicon technology
8232
Field-effect technology
8234
MIS technology
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
52
Arrangements for conducting electric current within the device in operation from one component to another
522
including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
532
characterised by the materials
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04
the substrate being a semiconductor body
08
including only semiconductor components of a single kind
085
including field-effect components only
088
the components being field-effect transistors with insulated gate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
14
including semiconductor components sensitive to infra-red radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
144
Devices controlled by radiation
146
Imager structures
H ELECTRICITY
04
ELECTRIC COMMUNICATION TECHNIQUE
N
PICTORIAL COMMUNICATION, e.g. TELEVISION
5
Details of television systems
30
Transforming light or analogous information into electric information
335
using solid-state image sensors [SSIS]
369
SSIS architecture; Circuitry associated therewith
H ELECTRICITY
04
ELECTRIC COMMUNICATION TECHNIQUE
N
PICTORIAL COMMUNICATION, e.g. TELEVISION
5
Details of television systems
30
Transforming light or analogous information into electric information
335
using solid-state image sensors [SSIS]
369
SSIS architecture; Circuitry associated therewith
374
Addressed sensors, e.g. MOS or CMOS sensors
H01L 21/768 (2006.01)
H01L 21/8234 (2006.01)
H01L 23/532 (2006.01)
H01L 27/00 (2006.01)
H01L 27/088 (2006.01)
H01L 27/146 (2006.01)
CPC
H01L 21/768
H01L 21/8234
H01L 23/532
H01L 27/00
H01L 27/088
H01L 27/146
Applicants
  • ソニーセミコンダクタソリューションズ株式会社 SONY SEMICONDUCTOR SOLUTIONS CORPORATION [JP/JP]; 神奈川県厚木市旭町四丁目14番1号 4-14-1, Asahi-cho, Atsugi-shi, Kanagawa 2430014, JP
Inventors
  • 羽根田 雅希 HANEDA, Masaki; JP
Agents
  • 特許業務法人酒井国際特許事務所 SAKAI INTERNATIONAL PATENT OFFICE; 東京都千代田区霞が関3丁目8番1号 虎の門三井ビルディング Toranomon Mitsui Building, 8-1, Kasumigaseki 3-chome, Chiyoda-ku, Tokyo 1000013, JP
Priority Data
2018-12152427.06.2018JP
Publication Language Japanese (JA)
Filing Language Japanese (JA)
Designated States
Title
(EN) SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
(FR) DISPOSITIF À SEMI-CONDUCTEUR ET SON PROCÉDÉ DE FABRICATION
(JA) 半導体装置及び半導体装置の製造方法
Abstract
(EN)
Provided is a semiconductor device in which the inter-wire capacity of wires disposed in an arbitrary layout is further reduced. The semiconductor device (1) is provided with: a first inter-wire insulating layer (120) which is disposed on a substrate (100) and includes a recess on the opposite side to the substrate; a first wire layer (130) disposed in the recess of the first inter-wire insulating layer; a sealing film (140) disposed along a recessed/protruding shape of the first wire layer and the first inter-wire insulating layer; a second inter-wire insulating layer (220) which is disposed on the first inter-wire insulating layer so as to cover the recess, and has a flat surface facing the recess; and an air gap (150) disposed between the second inter-wire insulating layer and the first wire layer and first inter-wire insulating layer.
(FR)
L'invention concerne un dispositif à semi-conducteur dans lequel la capacité inter-fils de fils disposés dans une disposition arbitraire est en outre réduite. Le dispositif à semi-conducteur comprend : une première couche isolante inter-fils (120) qui est disposée sur un substrat (100) et comprend un évidement sur le côté opposé au substrat ; une première couche de fil (130) disposée dans l'évidement de la première couche isolante inter-fils ; un film d'étanchéité (140) disposé le long d'une forme évidée/saillante de la première couche de fil et de la première couche isolante inter-fils ; une seconde couche isolante inter-fils (220) qui est disposée sur la première couche isolante inter-fils de manière à recouvrir l'évidement, et a une surface plate faisant face à l'évidement ; et un entrefer (150) disposé entre la seconde couche isolante inter-fils et la première couche de fil et la première couche isolante inter-fils.
(JA)
任意のレイアウトで設けられた配線の配線間容量がより低減された半導体装置を提供する。基板(100)上に設けられ、前記基板と反対側に凹部を有する第1配線間絶縁層(120)と、前記第1配線間絶縁層の前記凹部の内部に設けられた第1配線層(130)と、前記第1配線層及び前記第1配線間絶縁層の凹凸形状に沿って設けられた封止膜(140)と、前記第1配線間絶縁層の上に前記凹部を覆うように設けられ、前記凹部に向き合う面が平坦である第2配線間絶縁層(220)と、前記第2配線間絶縁層と、前記第1配線層及び前記第1配線間絶縁層との間に設けられた空隙(150)と、を備える、半導体装置(1)。
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