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1. WO2020004021 - BI-DIRECTIONAL SWITCH ELEMENT

Publication Number WO/2020/004021
Publication Date 02.01.2020
International Application No. PCT/JP2019/023188
International Filing Date 12.06.2019
IPC
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
334
Multistep processes for the manufacture of devices of the unipolar type
335
Field-effect transistors
338
with a Schottky gate
C CHEMISTRY; METALLURGY
30
CRYSTAL GROWTH
B
SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
29
Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
10
Inorganic compounds or compositions
38
Nitrides
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
334
Multistep processes for the manufacture of devices of the unipolar type
335
Field-effect transistors
337
with a PN junction gate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
34
the devices having semiconductor bodies not provided for in groups H01L21/06, H01L21/16, and H01L21/18159
36
Deposition of semiconductor materials on a substrate, e.g. epitaxial growth
365
using reduction or decomposition of a gaseous compound yielding a solid condensate, i.e. chemical deposition
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
778
with two-dimensional charge carrier gas channel, e.g. HEMT
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
80
with field effect produced by a PN or other rectifying junction gate
808
with a PN junction gate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
80
with field effect produced by a PN or other rectifying junction gate
812
with a Schottky gate
H01L 21/338 (2006.01)
C30B 29/38 (2006.01)
H01L 21/337 (2006.01)
H01L 21/365 (2006.01)
H01L 29/778 (2006.01)
H01L 29/808 (2006.01)
CPC
C30B 29/38
H01L 29/778
H01L 29/808
H01L 29/812
Applicants
  • パナソニックIPマネジメント株式会社 PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD. [JP/JP]; 大阪府大阪市中央区城見2丁目1番61号 1-61, Shiromi 2-chome, Chuo-ku, Osaka-shi, Osaka 5406207, JP
Inventors
  • 野村 雅則 NOMURA, Masanori; --
  • 上野 弘明 UENO, Hiroaki; --
  • 木下 雄介 KINOSHITA, Yusuke; --
  • 山田 康博 YAMADA, Yasuhiro; --
  • 石田 秀俊 ISHIDA, Hidetoshi; --
Agents
  • 特許業務法人北斗特許事務所 HOKUTO PATENT ATTORNEYS OFFICE; 大阪府大阪市北区梅田一丁目12‐17梅田スクエアビル Umeda Square Bldg., 12-17, Umeda 1-chome, Kita-ku, Osaka-shi, Osaka 5300001, JP
Priority Data
2018-12545229.06.2018JP
Publication Language Japanese (JA)
Filing Language Japanese (JA)
Designated States
Title
(EN) BI-DIRECTIONAL SWITCH ELEMENT
(FR) ÉLÉMENT DE COMMUTATION BIDIRECTIONNEL
(JA) 双方向スイッチ素子
Abstract
(EN)
The present invention addresses the problem of reducing current collapse. A bi-directional switch element (1) includes a substrate (2), an AlzGa1-zN layer (GaN layer 6), an AlbGa1-bN layer (first AlGaN layer 7), a first source electrode (S1), a first gate electrode (G1), a second gate electrode (G2), a second source electrode (S2), a p-type Alx1Ga1-x1N layer (first p-type AlGaN layer 81), a p-type Alx2Ga1-x2N layer (second p-type AlGaN layer 82), an AlyGa1-yN layer (second AlGaN layer 5), and an AlwGa1-wN layer (third AlGaN layer 4). The AlzGa1-zN layer is formed on the substrate (2). The AlbGa1-bN layer is formed on the AlzGa1-zN layer. The AlyGa1-yN layer is interposed between the substrate (2) and the AlzGa1-zN layer. The AlwGa1-wN layer is interposed between the substrate (2) and the AlyGa1-yN layer, and has a concentration of C that is higher than that of the AlyGa1-yN layer.
(FR)
La présente invention aborde le problème de la réduction d'une chute de courant. Un élément de commutation bidirectionnel (1) comprend un substrat (2), une couche d'AlzGa1-zN (couche de GaN 6), une couche d'AlbGa1-bN (première couche d'AlGaN 7), une première électrode source (S1), une première électrode grille (G1), une seconde électrode grille (G2), une seconde électrode source (S2), une couche d'Alx1Ga1-x1N de type p (première couche d'AlGaN de type p 81), une couche d'Alx2Ga1-x2N de type p (seconde couche d'AlGaN de type p 82), une couche d'AlyGa1-yN (deuxième couche d'AlGaN 5), et une couche d'AlwGa1-wN (troisième couche d'AlGaN 4). La couche d'AlzGa1-zN est formée sur le substrat (2). La couche d'AlbGa1-bN est formée sur la couche d'AlzGa1-zN. La couche d'AlyGa1-yN est interposée entre le substrat (2) et la couche d'AlzGa1-zN. La couche d'AlwGa1-wN est interposée entre le substrat (2) et la couche d'AlyGa1-yN, et a une concentration de C qui est supérieure à celle de la couche d'AlyGa1-yN.
(JA)
本開示の課題は、電流コラプスを抑制することである。双方向スイッチ素子(1)は、基板(2)、AlGa1-zN層(GaN層6)、AlGa1-bN層(第1のAlGaN層7)、第1のソース電極(S1)、第1のゲート電極(G1)、第2のゲート電極(G2)、第2のソース電極(S2)、p型Alx1Ga1-x1N層(第1のp型AlGaN層81)、p型Alx2Ga1-x2N層(第2のp型AlGaN層82)、AlGa1-yN層(第2のAlGaN層5)、及びAlGa1-wN層(第3のAlGaN層4)を備える。AlGa1-zN層は、基板(2)上に形成されている。AlGa1-bN層は、AlGa1-zN層上に形成されている。AlGa1-yN層は、基板(2)とAlGa1-zN層との間に介在している。AlGa1-wN層は、基板(2)とAlGa1-yN層との間に介在し、AlGa1-yN層よりもCの濃度が高い。
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