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1. WO2020004011 - SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD

Publication Number WO/2020/004011
Publication Date 02.01.2020
International Application No. PCT/JP2019/023103
International Filing Date 11.06.2019
IPC
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
71
Manufacture of specific parts of devices defined in group H01L21/7086
768
Applying interconnections to be used for carrying current between separate components within a device
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30
Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
31
to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After-treatment of these layers; Selection of materials for these layers
3205
Deposition of non-insulating-, e.g. conductive- or resistive-, layers, on insulating layers; After-treatment of these layers
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
52
Arrangements for conducting electric current within the device in operation from one component to another
522
including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
52
Arrangements for conducting electric current within the device in operation from one component to another
522
including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
532
characterised by the materials
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
14
including semiconductor components sensitive to infra-red radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
144
Devices controlled by radiation
146
Imager structures
H01L 21/768 (2006.01)
H01L 21/3205 (2006.01)
H01L 23/522 (2006.01)
H01L 23/532 (2006.01)
H01L 27/146 (2006.01)
CPC
H01L 21/3205
H01L 21/768
H01L 23/522
H01L 23/532
H01L 27/146
Applicants
  • ソニーセミコンダクタソリューションズ株式会社 SONY SEMICONDUCTOR SOLUTIONS CORPORATION [JP/JP]; 神奈川県厚木市旭町四丁目14番1号 4-14-1, Asahicho, Atsugi-shi, Kanagawa 2430014, JP
Inventors
  • 川島 寛之 KAWASHIMA, Hiroyuki; JP
  • 中邑 良一 NAKAMURA, Ryoichi; JP
  • 香川 恵永 KAGAWA, Yoshihisa; JP
  • 小林 悠作 KOBAYASHI, Yuusaku; JP
Agents
  • 特許業務法人つばさ国際特許事務所 TSUBASA PATENT PROFESSIONAL CORPORATION; 東京都新宿区新宿1丁目15番9号さわだビル3階 3F, Sawada Building, 15-9, Shinjuku 1-chome, Shinjuku-ku, Tokyo 1600022, JP
Priority Data
2018-12392729.06.2018JP
Publication Language Japanese (JA)
Filing Language Japanese (JA)
Designated States
Title
(EN) SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD
(FR) DISPOSITIF À SEMI-CONDUCTEUR ET PROCÉDÉ DE FABRICATION DE DISPOSITIF À SEMI-CONDUCTEUR
(JA) 半導体装置および半導体装置の製造方法
Abstract
(EN)
A semiconductor device according to one embodiment of the present disclosure is provided with: a first substrate having a first bonding section; and a second substrate having a second bonding section which is bonded to the first bonding section. The first substrate further includes a first multilayer wiring layer which is electrically connected to the first bonding section via a first insulating layer and in which one surface of a first wiring formed on a side closest to the bonding surface with respect to the second substrate faces the first insulating layer, and the other surface opposite to the one surface is in contact with a second insulating layer having a dielectric constant lower than that of the first insulating layer.
(FR)
Un dispositif à semi-conducteur selon un mode de réalisation de la présente invention comprend : un premier substrat ayant une première section de liaison ; et un second substrat ayant une seconde section de liaison qui est liée à la première section de liaison. Le premier substrat comprend en outre une première couche de câblage multicouche qui est électriquement connectée à la première section de liaison par l'intermédiaire d'une première couche isolante et dans laquelle une surface d'un premier câblage formé sur un côté le plus proche de la surface de liaison par rapport au second substrat fait face à la première couche isolante, et l'autre surface opposée à la première surface est en contact avec une seconde couche isolante ayant une constante diélectrique inférieure à celle de la première couche isolante.
(JA)
本開示の一実施形態の半導体装置は、第1の接合部を有する第1の基板と、第1の接合部と接合される第2の接合部を有する第2の基板とを備え、第1の基板はさらに第1の絶縁層を介して第1の接合部と電気的に接続されると共に、最も第2の基板との接合面側に形成された第1の配線の一の面が第1の絶縁層に面し、一の面に対向する他の面が第1の絶縁層よりも比誘電率の低い第2の絶縁層に接している第1の多層配線層を有する。
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