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1. WO2020003920 - ADHESIVE TAPE FOR SEMICONDUCTOR PROCESSING AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE

Publication Number WO/2020/003920
Publication Date 02.01.2020
International Application No. PCT/JP2019/022165
International Filing Date 04.06.2019
IPC
[IPC code unknown for C09J 7/29]
B PERFORMING OPERATIONS; TRANSPORTING
32
LAYERED PRODUCTS
B
LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
27
Layered products essentially comprising synthetic resin
C CHEMISTRY; METALLURGY
09
DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
J
ADHESIVES; NON-MECHANICAL ASPECTS OF ADHESIVE PROCESSES IN GENERAL; ADHESIVE PROCESSES NOT PROVIDED FOR ELSEWHERE; USE OF MATERIALS AS ADHESIVES
201
Adhesives based on unspecified macromolecular compounds
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30
Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
301
to subdivide a semiconductor body into separate parts, e.g. making partitions
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30
Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
302
to change the physical characteristics of their surfaces, or to change their shape, e.g. etching, polishing, cutting
304
Mechanical treatment, e.g. grinding, polishing, cutting
C09J 7/29 (2018.01)
B32B 27/00 (2006.01)
C09J 201/00 (2006.01)
H01L 21/301 (2006.01)
H01L 21/304 (2006.01)
Applicants
  • リンテック株式会社 LINTEC CORPORATION [JP/JP]; 東京都板橋区本町23-23 23-23 Honcho, Itabashi-ku, Tokyo 1730001, JP
Inventors
  • 愛澤 和人 AIZAWA, Kazuto; JP
  • 前田 淳 MAEDA, Jun; JP
Agents
  • 前田・鈴木国際特許業務法人 MAEDA & SUZUKI; 東京都千代田区一ツ橋2丁目5番5号 岩波書店一ツ橋ビル8階 8F, Iwanami Shoten Hitotsubashi Bldg., 5-5, Hitotsubashi 2-chome, Chiyoda-ku, Tokyo 1010003, JP
Priority Data
2018-12112926.06.2018JP
Publication Language Japanese (JA)
Filing Language Japanese (JA)
Designated States
Title
(EN) ADHESIVE TAPE FOR SEMICONDUCTOR PROCESSING AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE
(FR) BANDE ADHÉSIVE POUR TRAITEMENT DE SEMI-CONDUCTEUR ET PROCÉDÉ DE PRODUCTION DE DISPOSITIF À SEMI-CONDUCTEUR
(JA) 半導体加工用粘着テープおよび半導体装置の製造方法
Abstract
(EN)
[Problem] To provide an adhesive tape for semiconductor processing, which is capable of suppressing cracks of a chip even if used in DBG or LDBG. [Solution] An adhesive tape for semiconductor processing, which comprises a base material, a buffer layer that is provided on at least one surface side of the base material, and an adhesive layer that is provided on the other surface side of the base material. This adhesive tape is configured such that: the buffer layer has a Young's modulus of 10-400 MPa at 23°C and a rupture energy of 1-9 MJ/m3; and the Young's modulus of the base material at 23°C is higher than the above-mentioned Young's modulus of the buffer layer.
(FR)
Le problème à la base de la présente invention concerne une bande adhésive pour le traitement de semi-conducteurs, qui est en mesure de supprimer les fissures d'une puce même si elle est utilisée en DBG ou en LDBG. La solution selon l'invention porte sur une bande adhésive pour traitement de semi-conducteur, qui comprend un matériau de base, une couche tampon qui est disposée sur au moins un côté de surface du matériau de base et une couche adhésive qui est disposée sur l'autre côté de surface du matériau de base. Cette bande adhésive est conçue de telle sorte que : la couche tampon présente un module de Young de 10-400 MPa à 23°C et une énergie de rupture de 1-9 MJ/m3 ; et le module de Young du matériau de base à 23°C est supérieur au module de Young susmentionné de la couche tampon.
(JA)
【課題】DBGまたはLDBGに用いても、チップのクラックを抑制できる半導体加工用粘着テープを提供すること。 【解決手段】基材と、当該基材の少なくとも一方の面側に設けられた緩衝層と、当該基材の他方の面側に設けられた粘着剤層とを有する粘着テープであって、前記緩衝層の23℃におけるヤング率が10~400MPaであり、破断エネルギーが1~9MJ/mであって、前記基材の23℃におけるヤング率が前記緩衝層のヤング率よりも大きい、半導体加工用粘着テープ。 
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