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1. WO2020003783 - IMAGING ELEMENT, IMAGING DEVICE, AND ELECTRONIC DEVICE

Publication Number WO/2020/003783
Publication Date 02.01.2020
International Application No. PCT/JP2019/019102
International Filing Date 14.05.2019
IPC
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
14
including semiconductor components sensitive to infra-red radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
144
Devices controlled by radiation
146
Imager structures
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30
Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
31
to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After-treatment of these layers; Selection of materials for these layers
3205
Deposition of non-insulating-, e.g. conductive- or resistive-, layers, on insulating layers; After-treatment of these layers
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
71
Manufacture of specific parts of devices defined in group H01L21/7086
768
Applying interconnections to be used for carrying current between separate components within a device
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
52
Arrangements for conducting electric current within the device in operation from one component to another
522
including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 27/146 (2006.01)
H01L 21/3205 (2006.01)
H01L 21/768 (2006.01)
H01L 23/522 (2006.01)
CPC
H01L 21/3205
H01L 21/768
H01L 23/522
H01L 27/146
Applicants
  • ソニーセミコンダクタソリューションズ株式会社 SONY SEMICONDUCTOR SOLUTIONS CORPORATION [JP/JP]; 神奈川県厚木市旭町四丁目14番1号 4-14-1, Asahi-cho, Atsugi-shi, Kanagawa 2430014, JP
Inventors
  • 森川 隆史 MORIKAWA Takafumi; JP
Agents
  • 山本 孝久 YAMAMOTO Takahisa; JP
  • 吉井 正明 YOSHII Masaaki; JP
Priority Data
2018-12404429.06.2018JP
Publication Language Japanese (JA)
Filing Language Japanese (JA)
Designated States
Title
(EN) IMAGING ELEMENT, IMAGING DEVICE, AND ELECTRONIC DEVICE
(FR) ÉLÉMENT D'IMAGERIE, DISPOSITIF D'IMAGERIE ET DISPOSITIF ÉLECTRONIQUE
(JA) 撮像素子、撮像装置、及び、電子機器
Abstract
(EN)
An imaging element including: a pixel array having pixels arranged in a matrix; and a plurality of vertical signal lines provided in each pixel column. The plurality of vertical signal lines provided in each pixel column are arranged in a plurality of wiring layers laminated upon the pixels and are arranged such that orthographic projections of the vertical signal lines on the plurality of wiring layers overlap. A connection section for connecting a vertical signal line corresponding to a pixel to that pixel is provided in the wiring layer. The pixel signals are retrieved from the vertical signal lines via the connection section.
(FR)
L'invention concerne un élément d'imagerie comprenant : un réseau de pixels ayant des pixels agencés dans une matrice ; et une pluralité de lignes de signal verticales disposées dans chaque colonne de pixels. La pluralité de lignes de signal verticales disposées dans chaque colonne de pixels sont agencées dans une pluralité de couches de câblage stratifiées sur les pixels et sont agencées de telle sorte que des projections orthographiques des lignes de signal verticales sur la pluralité de couches de câblage se chevauchent. Une section de connexion pour connecter une ligne de signal verticale correspondant à un pixel à ce pixel est disposée dans la couche de câblage. Les signaux de pixel sont extraits des lignes de signal verticales par l'intermédiaire de la section de connexion.
(JA)
撮像素子は、画素が行列状に配列された画素アレイ部と、画素列単位で設けられた複数の垂直信号線とを含んでおり、画素列単位で設けられた複数の垂直信号線は、画素上に積層された複数の配線層に配置されていると共に、複数の配線層に対する垂直信号線の正射影が重なるように配置されており、配線層には、画素に対応する垂直信号線を画素に接続するための接続部が設けられており、画素の信号は、接続部を経由して垂直信号線から取り出される。
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