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1. (WO2020000079) CLOCK RECOVERY DEVICE WITH STATE MACHINE CONTROLLER
Latest bibliographic data on file with the International BureauSubmit observation

Pub. No.: WO/2020/000079 International Application No.: PCT/CA2019/000062
Publication Date: 02.01.2020 International Filing Date: 13.05.2019
IPC:
H04L 7/033 (2006.01)
H ELECTRICITY
04
ELECTRIC COMMUNICATION TECHNIQUE
L
TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
7
Arrangements for synchronising receiver with transmitter
02
Speed or phase control by the received code signals, the signals containing no special synchronisation information
033
using the transitions of the received signal to control the phase of the synchronising-signal- generating means, e.g. using a phase-locked loop
Applicants:
MICROSEMI SEMICONDUCTOR ULC [CA/CA]; 400 March Road Kanata, Ontario K2K 3H4, CA
Inventors:
HADDAD, Tariq; CA
LI, Xihao; CA
FRIESEN, Robert; CA
Agent:
LYNDS, Grant; c/o Marks & Clerk Canada PO Box 957, Station B Ottawa, Ontario K1P 5S7, CA
Priority Data:
16/058,01508.08.2018US
62/689,85526.06.2018US
Title (EN) CLOCK RECOVERY DEVICE WITH STATE MACHINE CONTROLLER
(FR) DISPOSITIF DE RÉCUPÉRATION D'HORLOGE À L'AIDE D'UN CONTRÔLEUR DE MACHINE À ÉTATS
Abstract:
(EN) A clock recovery device recovers frequency and timing information from an incoming packet stream over asynchronous packet networks. A phase locked loop (PLL) block has predefined states and includes a type II PLL. One of the states involves type II PLL operation. A state machine controller for controls the transition between the predefined states in response to changes in the incoming packet stream. A controlled oscillator is responsive to the PLL block to generate an output signal.
(FR) L'invention concerne un dispositif de récupération d'horloge qui récupère des informations de fréquence et de synchronisation à partir d'un flux de paquets entrant sur des réseaux de paquets asynchrones. Un bloc à boucle de verrouillage de phase (PLL) présente des états prédéfinis et comprend une PLL de type II. L'un des états implique un fonctionnement PLL de type II. Un contrôleur de machine à états commande la transition entre les états prédéfinis en réponse à des changements dans le flux de paquets entrant. Un oscillateur commandé réagit au bloc PLL afin de générer un signal de sortie.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)