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1. WO2019226448 - SEMICONDUCTOR MEMORY DEVICE HAVING PLURAL CHIPS CONNECTED BY HYBRID BONDING METHOD

Publication Number WO/2019/226448
Publication Date 28.11.2019
International Application No. PCT/US2019/032588
International Filing Date 16.05.2019
IPC
H01L 27/108 2006.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
10including a plurality of individual components in a repetitive configuration
105including field-effect components
108Dynamic random access memory structures
CPC
G11C 11/408
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21using electric elements
34using semiconductor devices
40using transistors
401forming cells needing refreshing or charge regeneration, i.e. dynamic cells
4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
407for memory cells of the field-effect type
408Address circuits
G11C 11/4085
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21using electric elements
34using semiconductor devices
40using transistors
401forming cells needing refreshing or charge regeneration, i.e. dynamic cells
4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
407for memory cells of the field-effect type
408Address circuits
4085Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
G11C 11/4091
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21using electric elements
34using semiconductor devices
40using transistors
401forming cells needing refreshing or charge regeneration, i.e. dynamic cells
4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
407for memory cells of the field-effect type
409Read-write [R-W] circuits 
4091Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
G11C 5/02
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
5Details of stores covered by G11C11/00
02Disposition of storage elements, e.g. in the form of a matrix array
G11C 5/025
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
5Details of stores covered by G11C11/00
02Disposition of storage elements, e.g. in the form of a matrix array
025Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
G11C 5/066
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
5Details of stores covered by G11C11/00
06Arrangements for interconnecting storage elements electrically, e.g. by wiring
066Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals
Applicants
  • MICRON TECHNOLOGY, INC. [US]/[US]
Inventors
  • SUKEKAWA, Mitsunari
Agents
  • ENG, Kimton
  • ANDKEN, Kerry Lee
  • FAUTH, Justen D.
  • ITO, Mika
  • HEGSTROM, Brandon
  • MA, Yue Matthew
  • QUECAN, Andrew F.
  • STERN, Ronald
  • SPAITH, Jennifer
  • CORDRAY, Michael S.
Priority Data
15/986,69722.05.2018US
Publication Language English (en)
Filing Language English (EN)
Designated States
Title
(EN) SEMICONDUCTOR MEMORY DEVICE HAVING PLURAL CHIPS CONNECTED BY HYBRID BONDING METHOD
(FR) DISPOSITIF DE MÉMOIRE À SEMI-CONDUCTEURS POURVU DE PLUSIEURS PUCES CONNECTÉES PAR UN PROCÉDÉ DE LIAISON HYBRIDE
Abstract
(EN) Disclosed herein is an apparatus that includes a first semiconductor chip including a plurality of memory cell arrays and a plurality of first bonding electrodes electrically connected to the memory cell arrays, and a second semiconductor chip including a logic circuits and a plurality of second bonding electrodes electrically connected to the logic circuits. The first and second semiconductor chips are stacked with each other so that each of the first bonding electrodes is electrically connected to an associated one of the second bonding electrodes.
(FR) La présente invention concerne un appareil qui comprend une première puce semi-conductrice comprenant une pluralité de réseaux de cellules de mémoire et une pluralité de premières électrodes de liaison connectées électriquement aux réseaux de cellules de mémoire, et une seconde puce semi-conductrice comprenant un circuit logique et une pluralité de secondes électrodes de liaison connectées électriquement aux circuits logiques. La première et la seconde puce semi-conductrice sont empilées l'une avec l'autre de telle sorte que chacune des premières électrodes de liaison soit électriquement connectée à une électrode associée parmi les secondes électrodes de liaison.
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