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1. WO2019223208 - FABRICATION METHOD FOR AMORPHOUS SILICON TFT SUBSTRATE

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Publication Number WO/2019/223208
Publication Date 28.11.2019
International Application No. PCT/CN2018/108074
International Filing Date 27.09.2018
IPC
H01L 21/77 2017.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
H01L 21/336 2006.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18the devices having semiconductor bodies comprising elements of group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
334Multistep processes for the manufacture of devices of the unipolar type
335Field-effect transistors
336with an insulated gate
H01L 29/786 2006.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66Types of semiconductor device
68controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76Unipolar devices
772Field-effect transistors
78with field effect produced by an insulated gate
786Thin-film transistors
CPC
H01L 27/1288
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
12the substrate being other than a semiconductor body, e.g. an insulating body
1214comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
1259Multistep manufacturing methods
1288employing particular masking sequences or specially adapted masks, e.g. half-tone mask
H01L 29/66757
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; ; Multistep manufacturing processes therefor
66Types of semiconductor device ; ; Multistep manufacturing processes therefor
66007Multistep manufacturing processes
66075of devices having semiconductor bodies comprising group 14 or group 13/15 materials
66227the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
66409Unipolar field-effect transistors
66477with an insulated gate, i.e. MISFET
66742Thin film unipolar transistors
6675Amorphous silicon or polysilicon transistors
66757Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
Applicants
  • 武汉华星光电技术有限公司 WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD. [CN]/[CN]
Inventors
  • 刘广辉 LIU, Guanghui
Agents
  • 深圳市德力知识产权代理事务所 COMIPS INTELLECTUAL PROPERTY OFFICE
Priority Data
201810488941.221.05.2018CN
Publication Language Chinese (zh)
Filing Language Chinese (ZH)
Designated States
Title
(EN) FABRICATION METHOD FOR AMORPHOUS SILICON TFT SUBSTRATE
(FR) PROCÉDÉ DE FABRICATION D'UN SUBSTRAT TFT EN SILICIUM AMORPHE
(ZH) 非晶硅TFT基板的制作方法
front page image
Abstract
(EN) A fabrication method for an amorphous silicon TFT substrate: first, forming a first photoresist layer that has photoresist patterns of three thicknesses by means of a first exposure process, and using the first photoresist layer to complete the patterning of an amorphous silicon layer, an N-type doped amorphous silicon layer, a first transparent conductive layer and a source/drain electrode metal layer by means of a three-time etching process and a two-time ashing process; then patterning a passivation layer by means of a second exposure process; finally, forming a second photoresist layer that has photoresist patterns of two thicknesses by means of a third exposure process, and using the second photoresist layer to complete the patterning of a second transparent conductive layer and a gate metal layer by means of a two-time etching process and a one-time ashing process.
(FR) L'invention concerne un procédé de fabrication d'un substrat TFT en silicium amorphe comprenant les étapes suivantes : tout d'abord, la formation d'une première couche de résine photosensible qui a des motifs de résine photosensible de trois épaisseurs au moyen d'un premier processus d'exposition, et l'utilisation de la première couche de résine photosensible pour achever la formation de motifs d'une couche de silicium amorphe, d'une couche de silicium amorphe dopée de type N, d'une première couche conductrice transparente et d'une couche métallique d'électrode source/drain au moyen d'un processus de gravure en trois temps et d'un processus de calcination en deux temps ; puis la formation d'un motif sur une couche de passivation au moyen d'un deuxième processus d'exposition ; enfin, la formation d'une seconde couche de résine photosensible qui a des motifs de résine photosensible de deux épaisseurs au moyen d'un troisième processus d'exposition, et l'utilisation de la seconde couche de résine photosensible pour achever la formation de motifs d'une seconde couche conductrice transparente et d'une couche métallique de grille au moyen d'un processus de gravure en deux temps et d'un processus de calcination unique.
(ZH) 一种非晶硅TFT基板的制作方法，首先经第一道曝光制程形成具有三个厚度的光阻图案的第一光阻层，并通过三次蚀刻制程和两次灰化制程，利用第一光阻层完成非晶硅层、N型掺杂非晶硅层、第一透明导电层及源漏极金属层这四层的图案化，然后经第二道曝光制程进行钝化层的图案化，最后经第三道曝光制程形成具有两个厚度的光阻图案的第二光阻层，通过两次蚀刻制程和一次灰化制程，利用第二光阻层完成第二透明导电层及栅极金属层这两层的图案化。
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