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1. WO2019215808 - METHOD FOR MANUFACTURING COLUMNAR SEMICONDUCTOR DEVICE

Publication Number WO/2019/215808
Publication Date 14.11.2019
International Application No. PCT/JP2018/017742
International Filing Date 08.05.2018
Chapter 2 Demand Filed 16.08.2019
IPC
H01L 21/336 2006.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18the devices having semiconductor bodies comprising elements of group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
334Multistep processes for the manufacture of devices of the unipolar type
335Field-effect transistors
336with an insulated gate
H01L 29/78 2006.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66Types of semiconductor device
68controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76Unipolar devices
772Field-effect transistors
78with field effect produced by an insulated gate
CPC
H01L 21/02238
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
02104Forming layers
02107Forming insulating materials on a substrate
02225characterised by the process for the formation of the insulating layer
02227formation by a process other than a deposition process
0223formation by oxidation, e.g. oxidation of the substrate
02233of the semiconductor substrate or a semiconductor layer
02236group IV semiconductor
02238silicon in uncombined form, i.e. pure silicon
H01L 21/02636
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
02104Forming layers
02365Forming inorganic semiconducting materials on a substrate
02612Formation types
02617Deposition types
02636Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
H01L 21/02639
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
02104Forming layers
02365Forming inorganic semiconducting materials on a substrate
02612Formation types
02617Deposition types
02636Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
02639Preparation of substrate for selective deposition
H01L 21/2252
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
18the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
22Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; ; Interactions between two or more impurities; Redistribution of impurities
225using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
2251Diffusion into or out of group IV semiconductors
2252using predeposition of impurities into the semiconductor surface, e.g. from a gaseous phase
H01L 21/30604
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
18the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
302to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
306Chemical or electrical treatment, e.g. electrolytic etching
30604Chemical etching
H01L 21/308
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
18the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
302to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
306Chemical or electrical treatment, e.g. electrolytic etching
308using masks
Applicants
  • ユニサンティス エレクトロニクス シンガポール プライベート リミテッド UNISANTIS ELECTRONICS SINGAPORE PTE. LTD. [SG]/[SG] (AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BE, BF, BG, BH, BJ, BN, BR, BW, BY, BZ, CA, CF, CG, CH, CI, CL, CM, CN, CO, CR, CU, CY, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, FR, GA, GB, GD, GE, GH, GM, GN, GQ, GR, GT, GW, HN, HR, HU, ID, IE, IL, IN, IR, IS, IT, JO, JP, KE, KG, KH, KM, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LT, LU, LV, LY, MA, MC, MD, ME, MG, MK, ML, MN, MR, MT, MW, MX, MY, MZ, NA, NE, NG, NI, NL, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SI, SK, SL, SM, SN, ST, SV, SY, SZ, TD, TG, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, UZ, VC, VN, ZA, ZM, ZW)
  • 舛岡 富士雄 MASUOKA Fujio [JP]/[JP] (US)
  • 原田 望 HARADA Nozomu [JP]/[JP] (US)
  • 菊池 善明 KIKUCHI Yoshiaki [JP]/[BE] (US)
Inventors
  • 舛岡 富士雄 MASUOKA Fujio
  • 原田 望 HARADA Nozomu
  • 菊池 善明 KIKUCHI Yoshiaki
Agents
  • 田中 伸一郎 TANAKA Shinichiro
  • 弟子丸 健 DESHIMARU Takeshi
  • ▲吉▼田 和彦 YOSHIDA Kazuhiko
  • 大塚 文昭 OHTSUKA Fumiaki
  • 西島 孝喜 NISHIJIMA Takaki
  • 須田 洋之 SUDA Hiroyuki
  • 上杉 浩 UESUGI Hiroshi
  • 近藤 直樹 KONDO Naoki
  • 那須 威夫 NASU Takeo
Priority Data
Publication Language Japanese (ja)
Filing Language Japanese (JA)
Designated States
Title
(EN) METHOD FOR MANUFACTURING COLUMNAR SEMICONDUCTOR DEVICE
(FR) PROCÉDÉ DE FABRICATION D'UN DISPOSITIF À SEMI-CONDUCTEUR EN COLONNE
(JA) 柱状半導体装置の製造方法
Abstract
(EN) A SiO2 layer 5 is formed on an i-layer substrate 2 so as to be located at the bottom of a Si column 3. Then, a gate HfO2 layer 11b is formed so as to surround the side surface of the Si column 3, and a gate TiN layer 12b is formed so as to surround the HfO2 layer 11b. Then, P+ layers 18, 32 which contain high concentrations of acceptor impurities and serve as a source and a drain, respectively, are formed simultaneously or separately on the exposed bottom side surface and the exposed top of the Si column 3 by a selective epitaxial crystal growth method. Thus, a SGT is formed on the i-layer substrate 2.
(FR) Selon l'invention, une couche de SiO2 5 est formée sur un substrat à i couches 2 de façon à se trouver au fond d'une colonne de Si 3. Puis, une couche de HfO2 11b de grille est formée de manière à entourer la surface latérale de la colonne de Si 3, et une couche de TiN 12b de grille est formée de façon à entourer la couche de HfO2 11b. Des couches P+ 18, 32 affichant de fortes concentrations d'impuretés acceptrices et servant respectivement de source et de drain sont ensuite formées simultanément ou séparément sur la surface latérale inférieure exposée et sur la partie supérieure exposée de la colonne de Si 3 par un procédé de croissance épitaxiale sélective de cristal. Un SGT est ainsi formé sur le substrat à i couches 2.
(JA) Si柱3の底部とi層基板2上にSiO2層5を形成する。そして、Si柱3の側面を囲みゲートHfO2層11bを形成し、HfO2層11bを囲みゲートTiN層12bを形成する。そして、露出したSi柱3の底部側面と、頂部に、同時または別々に、選択エピタキシャル結晶成長法によりソース、ドレインとなるアクセプタ不純物を高濃度に含んだP+層18、32を形成する。これにより、i層基板2上にSGTを形成する。
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