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1. WO2019213654 - A TIME-TO-DIGITAL CONVERTER CIRCUIT

Publication Number WO/2019/213654
Publication Date 07.11.2019
International Application No. PCT/US2019/030892
International Filing Date 06.05.2019
IPC
H03M 1/50 2006.1
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
MCODING, DECODING OR CODE CONVERSION, IN GENERAL
1Analogue/digital conversion; Digital/analogue conversion
12Analogue/digital converters
50with intermediate conversion to time interval
H03L 7/197 2006.1
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
7Automatic control of frequency or phase; Synchronisation
06using a reference signal applied to a frequency- or phase-locked loop
16Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
18using a frequency divider or counter in the loop
197a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
CPC
G04F 10/005
GPHYSICS
04HOROLOGY
FTIME-INTERVAL MEASURING
10Apparatus for measuring unknown time intervals by electric means
005Time-to-digital converters [TDC]
H03L 7/085
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
7Automatic control of frequency or phase; Synchronisation
06using a reference signal applied to a frequency- or phase-locked loop
08Details of the phase-locked loop
085concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
H03L 7/197
HELECTRICITY
03BASIC ELECTRONIC CIRCUITRY
LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
7Automatic control of frequency or phase; Synchronisation
06using a reference signal applied to a frequency- or phase-locked loop
16Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
18using a frequency divider or counter in the loop
197a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
Applicants
  • TEXAS INSTRUMENTS INCORPORATED [US]/[US]
  • TEXAS INSTRUMENTS JAPAN LIMITED [JP]/[JP] (JP)
Inventors
  • YAO, Henry
  • PAREKH, Sinjeet, Dhanvantray
Agents
  • DAVIS Jr., Michael, A.
  • PESSETTO, John
Priority Data
15/991,02029.05.2018US
62/666,82204.05.2018US
Publication Language English (en)
Filing Language English (EN)
Designated States
Title
(EN) A TIME-TO-DIGITAL CONVERTER CIRCUIT
(FR) CIRCUIT DE CONVERTISSEUR TEMPS-NUMÉRIQUE
Abstract
(EN) A time-to-digital converter circuit (100) includes a logic gate (130) configured to receive a first trigger signal indicative of a first clock signal and a second trigger signal indicative of a second clock signal. The logic gate (130) is configured to generate a logic gate output signal responsive to the earlier of the first or second trigger signals to be a logic high. A synchronization circuit (133) is coupled to the logic gate (130) and is configured to synchronize the logic gate output signal to a third clock to produce a synchronization output signal. A counter circuit (150, 158) counts pulses of the synchronization output signal.
(FR) La présente invention concerne un circuit convertisseur temps-numérique (100) qui comprend une porte logique (130) configurée de sorte à recevoir un premier signal de déclenchement indiquant un premier signal d'horloge et un second signal de déclenchement indiquant un second signal d'horloge. La porte logique (130) est configurée de sorte à générer un signal de sortie de porte logique en réponse à l'avance des premier ou second signaux de déclenchement de sorte à être une logique élevée. Un circuit de synchronisation (133) est couplé à la porte logique (130) et est configuré de sorte à synchroniser le signal de sortie de porte logique avec une troisième horloge pour produire un signal de sortie de synchronisation. Un circuit compteur (150, 158) compte des impulsions du signal de sortie de synchronisation.
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