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1. WO2019211697 - SEMICONDUCTOR DEVICE

Publication Number WO/2019/211697
Publication Date 07.11.2019
International Application No. PCT/IB2019/053299
International Filing Date 22.04.2019
IPC
G06F 12/0893 2016.1
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
12Accessing, addressing or allocating within memory systems or architectures
02Addressing or allocation; Relocation
08in hierarchically structured memory systems, e.g. virtual memory systems
0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
0893Caches characterised by their organisation or structure
G11C 5/14 2006.1
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
5Details of stores covered by group G11C11/63
14Power supply arrangements
G11C 7/04 2006.1
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
7Arrangements for writing information into, or reading information out from, a digital store
04with means for avoiding disturbances due to temperature effects
G11C 11/405 2006.1
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21using electric elements
34using semiconductor devices
40using transistors
401forming cells needing refreshing or charge regeneration, i.e. dynamic cells
403with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
405with three charge-transfer gates, e.g. MOS transistors, per cell
G11C 11/4074 2006.1
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21using electric elements
34using semiconductor devices
40using transistors
401forming cells needing refreshing or charge regeneration, i.e. dynamic cells
4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
407for memory cells of the field-effect type
4074Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
H01L 21/8242 2006.1
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78with subsequent division of the substrate into plural individual devices
82to produce devices, e.g. integrated circuits, each consisting of a plurality of components
822the substrate being a semiconductor, using silicon technology
8232Field-effect technology
8234MIS technology
8239Memory structures
8242Dynamic random access memory structures (DRAM)
CPC
G06F 12/0893
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
12Accessing, addressing or allocating within memory systems or architectures
02Addressing or allocation; Relocation
08in hierarchically structured memory systems, e.g. virtual memory systems
0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
0893Caches characterised by their organisation or structure
G11C 11/405
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21using electric elements
34using semiconductor devices
40using transistors
401forming cells needing refreshing or charge regeneration, i.e. dynamic cells
403with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
405with three charge-transfer gates, e.g. MOS transistors, per cell
G11C 11/4074
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21using electric elements
34using semiconductor devices
40using transistors
401forming cells needing refreshing or charge regeneration, i.e. dynamic cells
4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
407for memory cells of the field-effect type
4074Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
G11C 5/14
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
5Details of stores covered by G11C11/00
14Power supply arrangements
G11C 7/04
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
7Arrangements for writing information into, or reading information out from, a digital store
04with means for avoiding disturbances due to temperature effects
H01L 21/8258
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78with subsequent division of the substrate into plural individual devices
82to produce devices, e.g. integrated circuits, each consisting of a plurality of components
8258the substrate being a semiconductor, using a combination of technologies covered by ; H01L21/8206, H01L21/8213; , H01L21/822, H01L21/8252, H01L21/8254 or H01L21/8256
Applicants
  • 株式会社半導体エネルギー研究所 SEMICONDUCTOR ENERGY LABORATORY CO., LTD. [JP]/[JP]
Inventors
  • 山崎舜平 YAMAZAKI, Shunpei
  • 加藤清 KATO, Kiyoshi
  • 木村肇 KIMURA, Hajime
  • 宮口厚 MIYAGUCHI, Atsushi
  • 井上達則 INOUE, Tatsunori
Priority Data
2018-08884602.05.2018JP
Publication Language Japanese (ja)
Filing Language Japanese (JA)
Designated States
Title
(EN) SEMICONDUCTOR DEVICE
(FR) DISPOSITIF À SEMI-CONDUCTEUR
(JA) 半導体装置
Abstract
(EN) Provided is a semiconductor device in which it is possible to change the storage region for each hierarchy level of a storage device. Specifically provided is a semiconductor device which has a control circuit and a storage device provided with a first and a second storage circuit. The first storage circuit is provided with a first capacitive element and a first transistor that functions to hold the charge stored in the first capacitive element. The second storage circuit is provided with a second transistor, a second capacitive element electrically connected to the gate of the second transistor, and a third transistor that functions to hold the charge stored in the second capacitive element. The first and third transistors are provided with a gate, a back gate, and a semiconductor layer having an oxide semiconductor. Adjusting the voltage applied to the first or the third transistor back gate changes the storage region of the first or the second storage circuit, respectively.
(FR) L'invention concerne un dispositif à semi-conducteur dans lequel il est possible de modifier la région de mémoire pour chaque niveau hiérarchique d'un dispositif de mémoire. L'invention concerne spécifiquement un dispositif à semi-conducteur qui comporte un circuit de commande et un dispositif de mémoire pourvu d'un premier et d'un second circuit de mémoire. Le premier circuit de mémoire est pourvu d'un premier élément capacitif et d'un premier transistor qui fonctionne pour maintenir la charge stockée dans le premier élément capacitif. Le second circuit de mémoire est pourvu d'un deuxième transistor, d'un second élément capacitif connecté électriquement à la grille du deuxième transistor, et d'un troisième transistor qui fonctionne pour maintenir la charge stockée dans le second élément capacitif. Les premier et troisième transistors sont pourvus d'une grille, d'une grille arrière et d'une couche semi-conductrice comportant un semi-conducteur à oxyde. Le réglage de la tension appliquée à la première ou à la troisième grille arrière de transistor modifie la région de mémoire du premier ou du second circuit de mémoire, respectivement.
(JA) 要約書 記憶装置の各階層の記憶領域の変更が可能な半導体装置を提供する。 第1および第2記憶回路を有する記憶装置と、制御回路と、を有する半導体装置で、第1記憶回路は、 第1容量素子と、 第1容量素子に保持される電荷を保持する機能を有する第1トランジスタと、 を有 し、 第2記憶回路は、 第2トランジスタと、 前記第2トランジスタのゲートに電気的に接続された第 2容量素子と、 第2容量素子に保持される電荷を保持する機能を有する第3トランジスタと、 を有す る。第1および第3トランジスタは、酸化物半導体を有する半導体層と、ゲートと、バックゲートと、 を有する。 第1又は第3トランジスタバックゲートに印加される電圧を調整することによって、 第1 又は第2記憶回路のそれぞれの記憶領域を変更する。
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