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1. WO2019193644 - THREE-DIMENSIONAL STRUCTURE FORMATION METHOD AND THREE-DIMENSIONAL STRUCTURE FORMATION DEVICE

Publication Number WO/2019/193644
Publication Date 10.10.2019
International Application No. PCT/JP2018/014234
International Filing Date 03.04.2018
IPC
H01L 21/56 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/06-H01L21/326162
56Encapsulations, e.g. encapsulating layers, coatings
H01L 21/60 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/06-H01L21/326162
60Attaching leads or other conductive members, to be used for carrying current to or from the device in operation
H05K 3/46 2006.01
HELECTRICITY
05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
3Apparatus or processes for manufacturing printed circuits
46Manufacturing multi-layer circuits
CPC
H01L 21/56
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, ; e.g. sealing of a cap to a base of a container
56Encapsulations, e.g. encapsulation layers, coatings
H01L 2224/18
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
2224Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
18High density interconnect [HDI] connectors; Manufacturing methods related thereto
H05K 3/46
HELECTRICITY
05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
3Apparatus or processes for manufacturing printed circuits
46Manufacturing multilayer circuits
Applicants
  • 株式会社FUJI FUJI CORPORATION [JP]/[JP]
Inventors
  • 稲垣 重義 INAGAKI, Shigeyoshi
Agents
  • 特許業務法人ネクスト NEXT INTERNATIONAL
  • 片岡 友希 KATAOKA, Tomoki
Priority Data
Publication Language Japanese (JA)
Filing Language Japanese (JA)
Designated States
Title
(EN) THREE-DIMENSIONAL STRUCTURE FORMATION METHOD AND THREE-DIMENSIONAL STRUCTURE FORMATION DEVICE
(FR) PROCÉDÉ ET DISPOSITIF DE FORMATION DE STRUCTURE TRIDIMENSIONNELLE
(JA) 3次元構造物形成方法、および3次元構造物形成装置
Abstract
(EN)
Provided is a method for forming a three-dimensional structure, the method comprising: a first formation step for forming a first plate-shaped structure using a curable resin; a second formation step for forming a second plate-shaped structure having a hole using a curable resin; a coating step for coating a curable resin on at least one surface of a surface of the first plate-shaped structure and a surface of the second plate-shaped structure on which a hole is open; a lamination step for laminating the first plate-shaped structure and the second plate-shaped structure such that an opening of the hole of the second plate-shaped structure is closed by the first plate-shaped structure and the hole is sealed; and a curing step for curing the curable resin that is coated in the coating step.
(FR)
L'invention concerne un procédé de formation d'une structure tridimensionnelle, le procédé comprenant : une première étape de formation consistant à former une première structure de forme plate au moyen d'une résine durcissable ; une seconde étape de formation consistant former une seconde structure de forme plate comportant un trou au moyen d'une résine durcissable ; une étape de revêtement consistant à appliquer une résine durcissable sur une surface de la première structure de forme plate et/ou sur une surface de la seconde structure de forme plate sur laquelle un trou est ouvert ; une étape de stratification consistant à stratifier la première structure de forme plate et la seconde structure de forme plate de telle sorte qu'une ouverture du trou de la seconde structure de forme plate est fermée par la première structure de forme plate et que le trou est scellé ; et une étape de durcissement consistant à faire durcir la résine durcissable revêtue à l'étape de revêtement.
(JA)
硬化性樹脂により第1の板状構造物を形成する第1形成工程と、硬化性樹脂により穴部を有する第2の板状構造物を形成する第2形成工程と、第1の板状構造物の面と、第2の板状構造物の穴部が開口する面との少なくとも一方の面に、硬化性樹脂を塗布する塗布工程と、第2の板状構造物の穴部の開口を第1の板状構造物により塞ぎ、穴部を密閉するように、第1の板状構造物と第2の板状構造物とを積層させる積層工程と、塗布工程において塗布された硬化性樹脂を硬化させる硬化工程とを含む3次元構造物形成方法。
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