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1. (WO2019067648) POWER NETWORK DC INTEGRITY CHECKS OF PCBS
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Pub. No.: WO/2019/067648 International Application No.: PCT/US2018/052997
Publication Date: 04.04.2019 International Filing Date: 26.09.2018
IPC:
G06F 17/50 (2006.01) ,H05K 1/02 (2006.01)
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
17
Digital computing or data processing equipment or methods, specially adapted for specific functions
50
Computer-aided design
H ELECTRICITY
05
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
K
PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
1
Printed circuits
02
Details
Applicants:
THE REGENTS OF THE UNIVERSITY OF CALIFORNIA [US/US]; Twelfth Floor 1111 Franklin Street Oakland, California 94607-5200, US
Inventors:
TAN, Sheldon; US
Agent:
POSEY, Ivan M.; US
MAK, Danton K.; US
BABBITT, William Thomas; US
SCHROEDER, Robert A.; US
Priority Data:
62/563,58726.09.2017US
Title (EN) POWER NETWORK DC INTEGRITY CHECKS OF PCBS
(FR) VÉRIFICATIONS D'INTÉGRITÉ DE COURANT CONTINU DE RÉSEAU ÉLECTRIQUE DE CARTES DE CIRCUITS IMPRIMÉS
Abstract:
(EN) A system and method for integrity analysis of a printed circuit board comprises a processor and a first set of instructions executable on the processor configured to use a two-dimensional mesh for the analysis of the printed circuit board to reduce the number of elements in a mesh representing the printed circuit board. A second set of instructions are executable on the processor are configured to use a resistive line to replace all vias and a third set of instructions are executable on the processor configured to approximate the contours of shapes in the printed circuit board to further reduce the number of elements.
(FR) L’invention concerne un système et un procédé d'analyse d'intégrité d'une carte de circuit imprimé qui comprennent un processeur et un premier ensemble d'instructions exécutables sur le processeur configurés pour utiliser un maillage bidimensionnel pour l'analyse de la carte de circuit imprimé afin de réduire le nombre d'éléments dans un maillage représentant la carte de circuit imprimé. Un second ensemble d'instructions, exécutables sur le processeur, est configuré pour utiliser une ligne résistive pour remplacer tous les trous d'interconnexion et un troisième ensemble d'instructions est exécutable sur le processeur configuré pour approximer les contours de formes dans la carte de circuit imprimé pour réduire davantage le nombre d'éléments.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)