Some content of this application is unavailable at the moment.
If this situation persist, please contact us atFeedback&Contact
1. (WO2019067575) MEMORY CELL WITH OXIDE CAP AND SPACER LAYER FOR PROTECTING A FLOATING GATE FROM A SOURCE IMPLANT
Latest bibliographic data on file with the International Bureau    Submit observation

Pub. No.: WO/2019/067575 International Application No.: PCT/US2018/052900
Publication Date: 04.04.2019 International Filing Date: 26.09.2018
IPC:
H01L 21/28 (2006.01) ,H01L 29/423 (2006.01) ,H01L 29/788 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
28
Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/268158
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
40
Electrodes
41
characterised by their shape, relative sizes or dispositions
423
not carrying the current to be rectified, amplified or switched
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
788
with floating gate
Applicants:
MICROCHIP TECHNOLOGY INCORPORATED [US/US]; 2355 West Chandler Blvd. Chandler, Arizona 85224-6199, US
Inventors:
HYMAS, Mel; US
CHEN, Bomy; US
STOM, Greg; US
WALLS, James; US
Agent:
SLAYDEN, Bruce W., II; US
Priority Data:
16/110,33023.08.2018US
62/564,17427.09.2017US
Title (EN) MEMORY CELL WITH OXIDE CAP AND SPACER LAYER FOR PROTECTING A FLOATING GATE FROM A SOURCE IMPLANT
(FR) CELLULE DE MÉMOIRE AVEC CAPUCHON D'OXYDE ET COUCHE D'ESPACEMENT POUR PROTÉGER UNE GRILLE FLOTTANTE D'UN IMPLANT SOURCE
Abstract:
(EN) A method of forming a memory cell, e.g., flash memory cell, may include (a) depositing polysilicon over a substrate, (b) depositing a mask over the polysilicon, (c) etching an opening in the mask to expose a surface of the polysilicon, (d) growing a floating gate oxide at the exposed polysilicon surface, (e) depositing additional oxide above the floating gate oxide, such that the floating gate oxide and additional oxide collectively define an oxide cap, (f) removing mask material adjacent the oxide cap, (g) etching away portions of the polysilicon uncovered by the oxide cap, wherein a remaining portion of the polysilicon defines a floating gate, and (h) depositing a spacer layer over the oxide cap and floating gate. The spacer layer may includes a shielding region aligned over at least one upwardly-pointing tip region of the floating gate, which helps protect such tip region(s) from a subsequent source implant process.
(FR) L'invention concerne un procédé de formation d'une cellule de mémoire, par exemple une cellule de mémoire flash, qui peut consister à : (a) déposer du polysilicium sur un substrat, (b) déposer un masque sur le polysilicium, (c) graver une ouverture dans le masque pour exposer une surface du polysilicium, (d) faire croître un oxyde de grille flottante au niveau de la surface de polysilicium exposée, (e) déposer un oxyde supplémentaire au-dessus de l'oxyde de grille flottante, de telle sorte que l'oxyde de grille flottante et l'oxyde supplémentaire définissent collectivement une coiffe d'oxyde, (f) retirer un matériau de masque adjacent à la coiffe d'oxyde, (g) graver des parties du polysilicium découvert par la coiffe d'oxyde, une partie restante du polysilicium définissant une grille flottante, et (h) déposer une couche d'espacement sur la coiffe d'oxyde et la grille flottante. La couche d'espacement peut comprendre une région de blindage alignée sur au moins une région de pointe orientée vers le haut de la grille flottante, ce qui aide à protéger une telle région de pointe (s) d'un processus d'implant source ultérieur.
front page image
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)