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1. (WO2019067371) METHOD TO NEUTRALIZE INCORRECTLY ORIENTED PRINTED DIODES
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Pub. No.: WO/2019/067371 International Application No.: PCT/US2018/052486
Publication Date: 04.04.2019 International Filing Date: 24.09.2018
IPC:
H05K 3/30 (2006.01) ,H01L 23/48 (2006.01) ,H05K 1/18 (2006.01)
H ELECTRICITY
05
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
K
PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
3
Apparatus or processes for manufacturing printed circuits
30
Assembling printed circuits with electric components, e.g. with resistor
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
48
Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H ELECTRICITY
05
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
K
PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
1
Printed circuits
18
Printed circuits structurally associated with non-printed electric components
Applicants:
NTHDEGREE TECHNOLOGIES WORLDWIDE INC. [US/US]; 1320 W. Auto Drive Tempe, Arizona 85284-1025, US
Inventors:
BLANCHARD, Richard A.; US
RAY, William Johnstone; US
Agent:
OGONOWSKY, Brian D.; US
Priority Data:
16/135,98219.09.2018US
62/564,05027.09.2017US
Title (EN) METHOD TO NEUTRALIZE INCORRECTLY ORIENTED PRINTED DIODES
(FR) PROCÉDÉ DE NEUTRALISATION DE DIODES IMPRIMÉES MAL ORIENTÉES
Abstract:
(EN) A programmable circuit includes an array of printed groups of microscopic transistors or diodes having pn junctions. The devices are pre-formed and printed as an ink and cured. The devices have a proper orientation and a reverse orientation after settling on a conductor layer. The devices are connected in parallel within small groups. To neutralize the reverse-oriented devices, a sufficient voltage is applied across the parallel-connected diodes to forward bias only the devices having the reverse orientation. This causes a sufficient current to flow through each of the reverse-orientated devices to destroy an electrical interface between an electrode of the devices and the conductor layer to create an open circuit, such that those devices do not affect a rectifying function of the devices in the group having the proper orientation. An interconnection conductor pattern may then interconnect the groups to form complex logic circuits.
(FR) Un circuit programmable comprend un réseau de groupes imprimés de transistors ou de diodes microscopiques ayant des jonctions PN. Les dispositifs sont préformés et imprimés en tant qu'encre et durcis. Les dispositifs ont une orientation correcte et une orientation inverse après tassement sur une couche conductrice. Les dispositifs sont connectés en parallèle au sein de petits groupes. Pour neutraliser les dispositifs orientés à l'inverse, une tension suffisante est appliquée aux bornes des diodes connectées en parallèle pour polariser vers l'avant uniquement les dispositifs ayant l'orientation inverse. Ceci provoque l'écoulement d'un courant suffisant à travers chacun des dispositifs orientés à l'inverse pour détruire une interface électrique entre une électrode des dispositifs et la couche conductrice en vue de créer un circuit ouvert, de sorte que ces dispositifs n'affectent pas une fonction de redressement des dispositifs dans le groupe ayant l'orientation correcte. Un motif conducteur d'interconnexion peut ensuite interconnecter les groupes pour former des circuits logiques complexes.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)