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1. (WO2019067194) SERIALIZER/DESERIALIZER (SERDES) LANES WITH LANE-BY-LANE DATARATE INDEPENDENCE
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Pub. No.: WO/2019/067194 International Application No.: PCT/US2018/050282
Publication Date: 04.04.2019 International Filing Date: 10.09.2018
IPC:
H03L 7/23 (2006.01) ,G06F 1/04 (2006.01) ,H04L 7/00 (2006.01) ,H03L 7/197 (2006.01)
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
L
AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
7
Automatic control of frequency or phase; Synchronisation
06
using a reference signal applied to a frequency- or phase-locked loop
16
Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
22
using more than one loop
23
with pulse counters or frequency dividers
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
1
Details not covered by groups G06F3/-G06F13/82
04
Generating or distributing clock signals or signals derived directly therefrom
H ELECTRICITY
04
ELECTRIC COMMUNICATION TECHNIQUE
L
TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
7
Arrangements for synchronising receiver with transmitter
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
L
AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
7
Automatic control of frequency or phase; Synchronisation
06
using a reference signal applied to a frequency- or phase-locked loop
16
Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
18
using a frequency divider or counter in the loop
197
a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
Applicants:
CAVIUM, LLC [US/US]; 5488 Marvell Lane Santa Clara, CA 95054, US
Inventors:
MENINGER, Scott E.; US
Agent:
MEAGHER, Timothy J.; US
SMITH, James, M.; US
BROOK, David, E.; US
CARROLL, Alice, O; US
WAKIMURA, Mary, Lou; US
Priority Data:
15/721,33429.09.2017US
Title (EN) SERIALIZER/DESERIALIZER (SERDES) LANES WITH LANE-BY-LANE DATARATE INDEPENDENCE
(FR) VOIES DE CONVERTISSEUR SÉRIE-PARALLÈLE/PARALLÈLE-SÉRIE (SERDES) AVEC INDÉPENDANCE DU DÉBIT DE DONNÉES ENTRE LES VOIES
Abstract:
(EN) A circuit and method enables multiple serializer/deserializer (SerDes) data lanes of a physical layer device (PHY) to operate across a broad range of diversified data rates that are independent from lane to lane. The multiple SerDes data lanes may operate at data rates independent from one another. A single low frequency clock is input to the PHY. A frequency of the single low frequency clock is increased via a common integer-N phase-locked loop (PLL) on the PHY to produce a higher frequency clock. Each of the SerDes data lanes is operated, independently, as a fractional-N PLL that employs the higher frequency clock. Use of the common integer-N PLL enables modulation noise of the fractional-N PLLs to be suppressed by moving the modulation noise to higher frequencies where a level of the modulation noise is filtered, avoiding use of high risk noise cancellation techniques.
(FR) L'invention concerne un circuit et un procédé qui permettent à de multiples voies de données de convertisseur série-parallèle/parallèle-série (SerDes) d'un dispositif de couche physique (PHY) de fonctionner sur une large plage de débits de données diversifiés qui sont indépendants entre les voies. Les multiples voies de données de SerDes peuvent fonctionner à des débits de données indépendants les uns des autres. Une seule horloge à basse fréquence est entrée dans le PHY. Une fréquence de l'horloge à basse fréquence unique est augmentée par le biais d'une boucle à verrouillage de phase (PLL) N entière commune sur le PHY pour produire une horloge de fréquence supérieure. Chacune des voies de données de SerDes fonctionne, indépendamment, sous la forme d'une PLL N fractionnaire qui utilise l'horloge de fréquence supérieure. L'utilisation de la PLL N entière commune permet de supprimer le bruit de modulation des PLL N fractionnaires en déplaçant le bruit de modulation vers des fréquences plus élevées où un niveau du bruit de modulation est filtré, évitant l'utilisation de techniques d'annulation de bruit à haut risque.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)