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1. (WO2019067141) INTER-CLUSTER COMMUNICATION OF LIVE-IN REGISTER VALUES
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Pub. No.: WO/2019/067141 International Application No.: PCT/US2018/048332
Publication Date: 04.04.2019 International Filing Date: 28.08.2018
IPC:
G06F 9/38 (2006.01) ,G06F 9/30 (2006.01)
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
9
Arrangements for programme control, e.g. control unit
06
using stored programme, i.e. using internal store of processing equipment to receive and retain programme
30
Arrangements for executing machine- instructions, e.g. instruction decode
38
Concurrent instruction execution, e.g. pipeline, look ahead
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
9
Arrangements for programme control, e.g. control unit
06
using stored programme, i.e. using internal store of processing equipment to receive and retain programme
30
Arrangements for executing machine- instructions, e.g. instruction decode
Applicants:
INTEL CORPORATION [US/US]; 2200 Mission College Boulevard Santa Clara, California 95054, US
Inventors:
PEDIADITAKI, Sofia; US
SCHUCHMAN, Ethan; US
BASU ROY CHOWDHURY, Rangeen; US
SHEVGOOR, Manjunath; US
Agent:
LANE, Thomas R.; US
Priority Data:
15/719,29028.09.2017US
Title (EN) INTER-CLUSTER COMMUNICATION OF LIVE-IN REGISTER VALUES
(FR) COMMUNICATION INTER-GRAPPES DE VALEURS DE REGISTRE EN DIRECT
Abstract:
(EN) Embodiments of apparatuses, methods, and systems for inter-cluster communication of live-in register values are described. In an embodiment, a processor includes a plurality of execution clusters. The processor also includes a cache memory in which to store a value to be produced by a first execution cluster of the plurality of execution clusters and consumed by a second execution cluster of the plurality of execution clusters. The cache memory is separate from a system memory hierarchy and a register set of the processor.
(FR) Les modes de réalisation de la présente invention concernent des appareils, des procédés, et des systèmes de communication inter-grappes de valeurs de registre en direct. Dans un mode de réalisation, un processeur comprend une pluralité de grappes d'exécution. Le processeur comprend également une mémoire cache dans laquelle stocker une valeur devant être produite au moyen d'une première grappe d'exécution de la pluralité de grappes d'exécution et consommée par une seconde grappe d'exécution de la pluralité de grappes d'exécution. La mémoire cache est séparée d'une hiérarchie de mémoire système et d'un ensemble de registres du processeur.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)