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1. (WO2019067129) BULK LAYER TRANSFER PROCESSING WITH BACKSIDE SILICIDATION
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Pub. No.: WO/2019/067129 International Application No.: PCT/US2018/048125
Publication Date: 04.04.2019 International Filing Date: 27.08.2018
IPC:
H01L 21/762 (2006.01) ,H01L 23/48 (2006.01) ,H01L 23/522 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
71
Manufacture of specific parts of devices defined in group H01L21/7086
76
Making of isolation regions between components
762
Dielectric regions
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
48
Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
52
Arrangements for conducting electric current within the device in operation from one component to another
522
including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
Applicants:
QUALCOMM INCORPORATED [US/US]; ATTN: International IP Administration 5775 Morehouse Drive San Diego, California 92121-1714, US
Inventors:
GOKTEPELI, Sinan; US
IMTHURN, George Pete; US
FANELLI, Stephen Alan; US
Agent:
LENKIN, Alan M.; US
LUTZ, Joseph; US
PARTOW-NAVID, Puya; US
FASHU-KANU, Alvin V.; US
Priority Data:
15/975,43409.05.2018US
62/565,49529.09.2017US
Title (EN) BULK LAYER TRANSFER PROCESSING WITH BACKSIDE SILICIDATION
(FR) TRAITEMENT DE TRANSFERT DE COUCHE MASSIVE AVEC SILICIURATION SUR LA FACE ARRIÈRE
Abstract:
(EN) A radio frequency integrated circuit (RFIC) includes a bulk semiconductor die. The RFIC also includes a first active/passive device on a first-side of the bulk semiconductor die, and a first deep trench isolation region extending from the first-side to a second-side opposite the first-side of the bulk semiconductor die. The RFIC also includes a contact layer on the second-side of the bulk semiconductor die. The RFIC further includes a second-side dielectric layer on the contact layer. The first deep trench isolation region may extend through the contact layer and into the second-side dielectric layer.
(FR) La présente invention concerne un circuit intégré radiofréquence (RFIC) qui comprend une puce semi-conductrice massive. Le RFIC comprend également un premier dispositif actif/passif sur un premier côté de la puce semi-conductrice massive, et une première région d'isolation de tranchée profonde s'étendant du premier côté à un second côté opposé au premier côté de la puce semi-conductrice massive. Le RFIC comprend également une couche de contact sur le second côté de la puce semi-conductrice massive. Le RFIC comprend en outre une couche diélectrique sur le second côté sur la couche de contact. La première région d'isolation de tranchée profonde peut s'étendre à travers la couche de contact et dans la couche diélectrique sur le second côté.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)