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1. (WO2019067102) THERMALLY CONSCIOUS STANDARD CELLS
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Pub. No.: WO/2019/067102 International Application No.: PCT/US2018/047158
Publication Date: 04.04.2019 International Filing Date: 21.08.2018
IPC:
H01L 27/02 (2006.01) ,H01L 21/02 (2006.01) ,H01L 21/31 (2006.01) ,H01L 23/373 (2006.01) ,H01L 23/532 (2006.01) ,H01L 27/118 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30
Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
31
to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After-treatment of these layers; Selection of materials for these layers
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
34
Arrangements for cooling, heating, ventilating or temperature compensation
36
Selection of materials, or shaping, to facilitate cooling or heating, e.g. heat sinks
373
Cooling facilitated by selection of materials for the device
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
52
Arrangements for conducting electric current within the device in operation from one component to another
522
including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
532
characterised by the materials
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04
the substrate being a semiconductor body
10
including a plurality of individual components in a repetitive configuration
118
Masterslice integrated circuits
Applicants:
QUALCOMM INCORPORATED [US/US]; Attn: International IP Administration 5775 Morehouse Drive San Digeo, California 92121-1714, US
Inventors:
ANDREWS, Sean Charles; US
LEE, Yong Ju; US
Agent:
ZHANG, Rongtian; US
Priority Data:
15/719,87729.09.2017US
Title (EN) THERMALLY CONSCIOUS STANDARD CELLS
(FR) CELLULES STANDARD À CONSCIENCE THERMIQUE
Abstract:
(EN) In certain aspects, an integrated circuit comprises a first standard cell having a height equal to a cell height, wherein the first standard cell comprises a first dielectric material in a first layer. The integrated circuit comprises a second standard cell having a height equal to the cell height and aligning with the first standard cell, wherein the second standard cell comprises the first dielectric material in the first layer. The integrated circuit further comprises a first thermal cell having a height equal to the cell height and aligning with and abutting to both the first standard cell and the second standard cell; and wherein the first thermal cell comprises a second dielectric material in the first layer having a higher thermal conductivity than that of the first dielectric material.
(FR) Certains aspects de l'invention concernent un circuit intégré comprenant une première cellule standard ayant une hauteur égale à une hauteur de cellule, la première cellule standard comprenant un premier matériau diélectrique dans une première couche. Le circuit intégré comprend une deuxième cellule standard ayant une hauteur égale à la hauteur de cellule et alignée avec la première cellule standard, la deuxième cellule standard comprenant le premier matériau diélectrique dans la première couche. Le circuit intégré comprend en outre une première cellule thermique ayant une hauteur égale à la hauteur de cellule et s'alignant avec la première cellule standard et la deuxième cellule standard et en butée contre celles-ci ; et la première cellule thermique comprenant un deuxième matériau diélectrique dans la première couche ayant une conductivité thermique supérieure à celle du premier matériau diélectrique.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)