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1. (WO2019067080) ATOMIC LAYER ETCHING OF METAL OXIDE
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Pub. No.: WO/2019/067080 International Application No.: PCT/US2018/044439
Publication Date: 04.04.2019 International Filing Date: 30.07.2018
IPC:
H01L 21/3065 (2006.01) ,H01L 21/3213 (2006.01) ,H01L 21/311 (2006.01) ,H01L 21/67 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30
Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
302
to change the physical characteristics of their surfaces, or to change their shape, e.g. etching, polishing, cutting
306
Chemical or electrical treatment, e.g. electrolytic etching
3065
Plasma etching; Reactive-ion etching
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30
Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
31
to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After-treatment of these layers; Selection of materials for these layers
3205
Deposition of non-insulating-, e.g. conductive- or resistive-, layers, on insulating layers; After-treatment of these layers
321
After-treatment
3213
Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30
Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
31
to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After-treatment of these layers; Selection of materials for these layers
3105
After-treatment
311
Etching the insulating layers
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
67
Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
Applicants:
LAM RESEARCH CORPORATION [US/US]; 4650 Cushing Parkway, M/S CA-1 Fremont, California 94538, US
Inventors:
FISCHER, Andreas; US
DRAEGER, Nerissa; US
Agent:
LEE, Michael; US
Priority Data:
15/717,07627.09.2017US
Title (EN) ATOMIC LAYER ETCHING OF METAL OXIDE
(FR) GRAVURE DE COUCHE ATOMIQUE D'OXYDE MÉTALLIQUE
Abstract:
(EN) A method for etching a metal oxide layer on a semiconductor substrate, comprising providing a plurality of cycles, is provided. Each cycle comprises exposing the metal oxide layer to a reactive hydrogen-containing gas or plasma to transform a part of the metal oxide layer into a layer of metal hydride, stopping the exposing the metal oxide layer to the reactive hydrogen-containing gas or plasma, heating the layer of metal hydride to at least a sublimation temperature to sublime the layer of metal hydride, and cooling the metal oxide layer to a temperature below the sublimation temperature.
(FR) L'invention concerne un procédé de gravure d'une couche d'oxyde métallique sur un substrat semi-conducteur, consistant à fournir une pluralité de cycles. Chaque cycle consiste à exposer la couche d'oxyde métallique à un gaz ou plasma contenant de l'hydrogène réactif pour transformer une partie de la couche d'oxyde métallique en une couche d'hydrure métallique, à arrêter l'exposition de la couche d'oxyde métallique au gaz ou au plasma contenant de l'hydrogène réactif, à chauffer la couche d'hydrure métallique à au moins une température de sublimation pour sublimer la couche d'hydrure métallique, et à refroidir la couche d'oxyde métallique à une température inférieure à la température de sublimation.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)