Some content of this application is unavailable at the moment.
If this situation persist, please contact us atFeedback&Contact
1. (WO2019067072) ADVANCED GRAPHICS POWER STATE MANAGEMENT
Latest bibliographic data on file with the International Bureau    Submit observation

Pub. No.: WO/2019/067072 International Application No.: PCT/US2018/043685
Publication Date: 04.04.2019 International Filing Date: 25.07.2018
IPC:
G06F 1/32 (2006.01) ,G06T 1/20 (2006.01)
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
1
Details not covered by groups G06F3/-G06F13/82
26
Power supply means, e.g. regulation thereof
32
Means for saving power
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
T
IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
1
General purpose image data processing
20
Processor architectures; Processor configuration, e.g. pipelining
Applicants:
INTEL CORPORATION [US/US]; 2200 Mission College Boulevard Santa Clara, California, US
Inventors:
SAMSON, Eric C.; US
RAMADOSS, Murali; US
BEUCHAT, Marc; US
Agent:
AGHEVLI, Ramin; US
Priority Data:
15/720,90629.09.2017US
Title (EN) ADVANCED GRAPHICS POWER STATE MANAGEMENT
(FR) GESTION D'ÉTAT D'ÉNERGIE GRAPHIQUE AVANCÉE
Abstract:
(EN) Methods and apparatus relating to advanced graphics Power State management are described. In one embodiment, measurement logic detects information about idle transitions and active transitions of a power-well of a processor. In turn, determination logic determines performance loss and/or energy gain based at least in part on the detected information and power-on latency of the power-well of the processor. Other embodiments are also disclosed and claimed.
(FR) L'invention concerne des procédés et un appareil relatifs à une gestion d'état d'énergie graphique avancée. Dans un mode de réalisation, une logique de mesure détecte des informations concernant les transitions inactives et les transitions actives d'un puits énergétique d'un processeur. À son tour, une logique de détermination détermine une perte de performance et/ou un gain d'énergie d'après au moins en partie les informations détectées et la latence de mise sous tension du puits énergétique du processeur. L'invention concerne également d'autres modes de réalisation.
front page image
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)