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1. (WO2019067053) MEMORY DECISION FEEDBACK EQUALIZER
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Pub. No.: WO/2019/067053 International Application No.: PCT/US2018/039818
Publication Date: 04.04.2019 International Filing Date: 27.06.2018
IPC:
G11C 7/10 (2006.01) ,G11C 8/12 (2006.01)
G PHYSICS
11
INFORMATION STORAGE
C
STATIC STORES
7
Arrangements for writing information into, or reading information out from, a digital store
10
Input/output (I/O) data interface arrangements, e.g. I/O data control circuits, I/O data buffers
G PHYSICS
11
INFORMATION STORAGE
C
STATIC STORES
8
Arrangements for selecting an address in a digital store
12
Group selection circuits, e.g. for memory block selection, chip selection, array selection
Applicants:
MICRON TECHNOLOGY, INC [US/US]; 8000 South Federal Way Boise, Idaho 83707, US
Inventors:
TAYLOR, Jennifer E.; US
SREERAMANENI, Raghukiran; US
Agent:
MANWARE, Robert A.; US
FLETCHER, Michael G.; US
YODER, Patrick S.; US
POWELL, W. Allen; US
RARIDEN, John M.; US
SWANSON, Tait R.; US
BAKKER, Jila; US
SINCLAIR, JR.,, Steven J.; US
OSTERHAUS, Matthew G.; US
DOOLEY, Matthew C.; US
KANTOR, Andrew L.; US
WIMMER, Lance G.; US
BELLAH, Sean J.; US
THOMAS, Jim; US
CORLEY, David; US
HENWOOD, Matthew C.; US
Priority Data:
15/716,16226.09.2017US
Title (EN) MEMORY DECISION FEEDBACK EQUALIZER
(FR) ÉGALISEUR À RÉTROACTION DE DÉCISION DE MÉMOIRE
Abstract:
(EN) A device (10) includes a decoder (204, 365) configured to receive an input signal. The decoder (204, 365) is configured to also output a control signal based on the input signal. The device (10) further includes an equalizer (202, 292, 356, 358, 434, 436, 448, 450) configured to receive a distorted bit as part of a data stream, receive the control signal, select a distortion correction factor based upon the control signal, apply the distortion correction factor to the distorted bit to offset inter-symbol interference from the data stream on the distorted input data to generate a modified value of the distorted bit, and generate a corrected bit based on the modified value of the distorted bit.
(FR) L'invention concerne un dispositif (10) qui comprend un décodeur (204, 365) configuré pour recevoir un signal d'entrée. Le décodeur (204, 365) est configuré pour émettre également un signal de commande sur la base du signal d'entrée. Le dispositif comprend en outre un égaliseur (202, 292, 356, 358, 434, 436, 448, 450) configuré pour recevoir un bit distordu en tant que partie d'un flux de données, recevoir le signal de commande, sélectionner un facteur de correction de distorsion sur la base du signal de commande, appliquer le facteur de correction de distorsion au bit distordu pour décaler un brouillage inter-symboles à partir du flux de données sur les données d'entrée distordues afin de générer une valeur modifiée du bit distordu, et générer un bit corrigé sur la base de la valeur modifiée du bit distordu.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)