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1. (WO2019067052) VOLTAGE REFERENCE COMPUTATIONS FOR MEMORY DECISION FEEDBACK EQUALIZERS
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Pub. No.: WO/2019/067052 International Application No.: PCT/US2018/039816
Publication Date: 04.04.2019 International Filing Date: 27.06.2018
IPC:
G11C 7/10 (2006.01)
G PHYSICS
11
INFORMATION STORAGE
C
STATIC STORES
7
Arrangements for writing information into, or reading information out from, a digital store
10
Input/output (I/O) data interface arrangements, e.g. I/O data control circuits, I/O data buffers
Applicants:
MICRON TECHNOLOGY, INC [US/US]; 8000 South Federal Way Boise, Idaho 83707, US
Inventors:
TAYLOR, Jennifer E.; US
SREERAMANENI, Raghukiran; US
Agent:
MANWARE, Robert A.; US
FLETCHER, Michael G.; US
YODER, Patrick S.; US
POWELL, W. Allen; US
RARIDEN, John M.; US
SWANSON, Tait R.; US
BAKKER, Jila; US
SINCLAIR, JR.,, Steven J.; US
OSTERHAUS, Matthew G.; US
DOOLEY, Matthew C.; US
HENWOOD, Matthew C.; US
KANTOR, Andrew L.; US
WIMMER, Lance G.; US
BELLAH, Sean J.; US
THOMAS, Jim; US
CORLEY, David; US
Priority Data:
15/716,13226.09.2017US
Title (EN) VOLTAGE REFERENCE COMPUTATIONS FOR MEMORY DECISION FEEDBACK EQUALIZERS
(FR) CALCULS DE RÉFÉRENCE DE TENSION POUR ÉGALISEURS DE RÉTROACTION DE DÉCISION DE MÉMOIRE
Abstract:
(EN) A device (10) includes a combinational circuit configured to create a one or more distortion correction factors used offset inter-symbol interference from a data stream on a distorted bit. The device (10) also includes a selection circuit (368) coupled to the combinational circuit. The selection circuit (368) includes a feedback pin (492) configured to receive a control signal and an output, wherein the selection circuit (368) is configured to select a first distortion correction factor of the one or more distortion correction factors based upon the control signal and transmit the first distortion correction factor from the output.
(FR) L'invention concerne un dispositif (10) qui comprend un circuit combinatoire configuré pour créer un ou plusieurs facteurs de correction de distorsion utilisés pour compenser un brouillage inter-symboles à partir d'un flux de données sur un bit distordu. Le dispositif (10) comprend également un circuit de sélection (368) couplé au circuit combinatoire. Le circuit de sélection (368) comprend une broche de rétroaction (492) configurée pour recevoir un signal de commande et une sortie, le circuit de sélection (368) est configuré pour sélectionner un premier facteur de correction de distorsion du ou des facteurs de correction de distorsion sur la base du signal de commande et transmettre le premier facteur de correction de distorsion à partir de la sortie.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)