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1. (WO2019066998) STACKED PACKAGE WITH ELECTRICAL CONNECTIONS CREATED USING HIGH THROUGHPUT ADDITIVE MANUFACTURING
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Pub. No.: WO/2019/066998 International Application No.: PCT/US2017/054682
Publication Date: 04.04.2019 International Filing Date: 30.09.2017
IPC:
H01L 23/367 (2006.01) ,H01L 23/04 (2006.01) ,H01L 23/00 (2006.01) ,H01L 23/42 (2006.01) ,H01L 23/40 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
34
Arrangements for cooling, heating, ventilating or temperature compensation
36
Selection of materials, or shaping, to facilitate cooling or heating, e.g. heat sinks
367
Cooling facilitated by shape of device
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
02
Containers; Seals
04
characterised by the shape
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
34
Arrangements for cooling, heating, ventilating or temperature compensation
42
Fillings or auxiliary members in containers selected or arranged to facilitate heating or cooling
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
34
Arrangements for cooling, heating, ventilating or temperature compensation
40
Mountings or securing means for detachable cooling or heating arrangements
Applicants:
EID, Feras [LB/US]; US
SWAN, Johanna M. [US/US]; US
LIFF, Shawna M. [US/US]; US
INTEL CORPORATION [US/US]; 2200 Mission College Boulevard Santa Clara, California 95054, US
Inventors:
EID, Feras; US
SWAN, Johanna M.; US
LIFF, Shawna M.; US
Agent:
ROJO, Estiven; US
BRASK, Justin K.; US
AUYEUNG, Al; US
BERNADICOU, Michael A.; US
BLAIR, Steven R.; US
BLANK, Eric S.; US
COFIELD, Michael A.; US
DANSKIN, Timothy A.; US
HALEVA, Aaron S.; US
MAKI, Nathan R.; US
MARLINK, Jeffrey S.; US
MOORE, Michael S.; US
PARKER, Wesley E.; US
PUGH, Joseph A.; US
RASKIN, Vladimir; US
STRAUSS, Ryan N.; US
WANG, Yuke; US
YATES, Steven D.; US
SULLIVAN, Stephen G.; US
Priority Data:
Title (EN) STACKED PACKAGE WITH ELECTRICAL CONNECTIONS CREATED USING HIGH THROUGHPUT ADDITIVE MANUFACTURING
(FR) BOÎTIER EMPILÉ DOTÉ DE CONNEXIONS ÉLECTRIQUES CRÉÉES À L'AIDE D'UNE FABRICATION ADDITIVE À HAUT DÉBIT
Abstract:
(EN) A device package and a method of forming the device package are described. The device package includes one or more dies disposed on a first substrate. The device packages further includes one or more interconnects vertically disposed on the first substrate, and a mold layer disposed over and around the first die, the one or more interconnects, and the first substrate. The device package has a second die disposed on a second substrate, wherein the first substrate is electrically coupled to the second substrate with the one or more interconnects, and wherein the one or more interconnects are directly disposed on at least one of a top surface of the first substrate and a bottom surface of the second substrate without an adhesive layer. The device package may include one or more interconnects having one or more different thicknesses or heights at different locations on the first substrate.
(FR) L'invention concerne un boîtier de dispositif et un procédé de formation du boîtier de dispositif. Le boîtier de dispositif comprend un ou plusieurs dés disposés sur un premier substrat. Les boîtiers de dispositif comprennent en outre une ou plusieurs interconnexions disposées verticalement sur le premier substrat, et une couche de moule disposée sur le premier dé, la ou les interconnexions, et le premier substrat et autour de ceux-ci. Le boîtier de dispositif comprend un second dé disposé sur un second substrat, le premier substrat étant électriquement couplé au second substrat au moyen de la ou des interconnexions, et la ou les interconnexions étant disposées directement sur une surface supérieure du premier substrat et/ou une surface inférieure du second substrat sans couche adhésive. Le boîtier de dispositif peut comprendre une ou plusieurs interconnexions ayant une ou plusieurs épaisseurs ou hauteurs différentes à différents emplacements sur le premier substrat.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)