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1. (WO2019066995) GROUP III-NITRIDE (III-N) DEVICES WITH IMPROVED RF PERFORMANCE AND THEIR METHODS OF FABRICATION
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Pub. No.: WO/2019/066995 International Application No.: PCT/US2017/054679
Publication Date: 04.04.2019 International Filing Date: 30.09.2017
IPC:
H01L 29/778 (2006.01) ,H01L 29/49 (2006.01) ,H01L 29/51 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
778
with two-dimensional charge carrier gas channel, e.g. HEMT
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
40
Electrodes
43
characterised by the materials of which they are formed
49
Metal-insulator semiconductor electrodes
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
40
Electrodes
43
characterised by the materials of which they are formed
49
Metal-insulator semiconductor electrodes
51
Insulating materials associated therewith
Applicants:
INTEL CORPORATION [US/US]; 2200 Mission College Blvd. Santa Clara, CA 95054, US
Inventors:
RADOSAVLJEVIC, Marko; US
DASGUPTA, Sansaptak; US
THEN, Han Wui; US
BAN, Ibrahim; US
FISCHER, Paul B.; US
Agent:
HOWARD, James M.; US
Priority Data:
Title (EN) GROUP III-NITRIDE (III-N) DEVICES WITH IMPROVED RF PERFORMANCE AND THEIR METHODS OF FABRICATION
(FR) DISPOSITIFS AU NITRURE DU GROUPE III (III-N) À PERFORMANCE RF AMÉLIORÉE ET LEURS PROCÉDÉS DE FABRICATION
Abstract:
(EN) A device including a III-N material is described. The device includes a transistor structure having a first layer including a first group III-nitride (III-N) material, a polarization charge inducing layer above the first layer, the polarization charge inducing layer including a second III-N material, a gate electrode above the polarization charge inducing layer and a source structure and a drain structure on opposite sides of the gate electrode. The device further includes a plurality of peripheral structures adjacent to transistor structure, where each of the peripheral structure includes the first layer, but lacks the polarization charge inducing layer, an insulating layer above the peripheral structure and the transistor structure, wherein the insulating layer includes a first dielectric material. A metallization structure, above the peripheral structure, is coupled to the transistor structure.
(FR) L'invention concerne un dispositif comprenant un matériau du groupe III-N. Le dispositif comprend une structure de transistor ayant une première couche comprenant un premier matériau de nitrure du groupe III (III-N), une couche induisant une charge de polarisation au-dessus de la première couche, la couche induisant une charge de polarisation comprenant un second matériau du groupe III-N, une électrode de grille au-dessus de la couche d'induction de charge de polarisation et une structure de source et une structure de drain sur des côtés opposés de l'électrode de grille. Le dispositif comprend en outre une pluralité de structures périphériques adjacentes à la structure de transistor, chacune de la structure périphérique comprenant la première couche, mais dépourvue de la couche inductrice de charge de polarisation, une couche isolante au-dessus de la structure périphérique et de la structure de transistor, la couche isolante comprenant un premier matériau diélectrique. Une structure de métallisation, au-dessus de la structure périphérique, est couplée à la structure de transistor.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)